From 35358d573bccd0776e55187564ccd6c72c9f9c34 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Fri, 27 Mar 2026 06:32:04 +0000
Subject: push/pop for segment registers has implicit memory access

---
 src/real_mode/mod.rs | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

(limited to 'src/real_mode')

diff --git a/src/real_mode/mod.rs b/src/real_mode/mod.rs
index c11cf00..7ac4c2e 100644
--- a/src/real_mode/mod.rs
+++ b/src/real_mode/mod.rs
@@ -8724,31 +8724,58 @@ fn read_operands<
             instruction.regs[0] = RegSpec::cs();
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operand_count = 1;
+
+            // see the comment on mem size as written in OperandCase::FS
+            instruction.mem_size = 2;
         }
         OperandCase::DS => {
             instruction.regs[0] = RegSpec::ds();
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operand_count = 1;
+
+            // see the comment on mem size as written in OperandCase::FS
+            instruction.mem_size = 2;
         }
         OperandCase::ES => {
             instruction.regs[0] = RegSpec::es();
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operand_count = 1;
+
+            // see the comment on mem size as written in OperandCase::FS
+            instruction.mem_size = 2;
         }
         OperandCase::SS => {
             instruction.regs[0] = RegSpec::ss();
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operand_count = 1;
+
+            // see the comment on mem size as written in OperandCase::FS
+            instruction.mem_size = 2;
         }
         OperandCase::FS => {
             instruction.regs[0] = RegSpec::fs();
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operand_count = 1;
+
+            // good grief. from the SDM:
+            //
+            // > If the source operand is a segment register (16 bits) and the operand size is
+            // > 64-bits, a zero-extended value is pushed on the stack; if the operand size is
+            // > 32-bits, either a zero-extended value is pushed on the stack or the segment selector
+            // > is written on the stack using a 16-bit move
+            //
+            // the memory size here really depends on the `Default` bit in the CS descriptor. if
+            // the default operand size is 64 bits (basically all long-mode code), the acccess is
+            // 8 bytes (zero extended). if the default operand size is 32 bits, this is more complex.
+            instruction.mem_size = 2;
         }
         OperandCase::GS => {
             instruction.regs[0] = RegSpec::gs();
             instruction.operands[0] = OperandSpec::RegRRR;
             instruction.operand_count = 1;
+
+            // see the comment on mem size as written in OperandCase::FS
+            instruction.mem_size = 2;
         }
         OperandCase::AL_Ib => {
             instruction.regs[0] =
-- 
cgit v1.1