From a049351c5d512710f557ffb45ee6391fc86a3dc6 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sun, 12 Apr 2026 01:03:47 +0000 Subject: fix table management instructions' ({l,s}{g,i,l}dt) mem_size these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know! --- src/real_mode/mod.rs | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'src/real_mode') diff --git a/src/real_mode/mod.rs b/src/real_mode/mod.rs index 7ac4c2e..559cac3 100644 --- a/src/real_mode/mod.rs +++ b/src/real_mode/mod.rs @@ -8087,7 +8087,7 @@ fn read_operands< } else { instruction.opcode = Opcode::SGDT; instruction.operand_count = 1; - instruction.mem_size = 63; + instruction.mem_size = 6; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 1 { @@ -8142,7 +8142,11 @@ fn read_operands< } else { instruction.opcode = Opcode::SIDT; instruction.operand_count = 1; - instruction.mem_size = 63; + // quoth SDM: + // > In non-64-bit modes, the 16-bit limit field of the register is stored in + // > the low 2 bytes of the memory location and the 32-bit base address is + // > stored in the high 4 bytes. + instruction.mem_size = 6; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 2 { @@ -8181,7 +8185,7 @@ fn read_operands< } else { instruction.opcode = Opcode::LGDT; instruction.operand_count = 1; - instruction.mem_size = 63; + instruction.mem_size = 6; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 3 { @@ -8245,7 +8249,7 @@ fn read_operands< } else { instruction.opcode = Opcode::LIDT; instruction.operand_count = 1; - instruction.mem_size = 63; + instruction.mem_size = 6; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 4 { -- cgit v1.1