From 723cbb61c1a8a7aa03fa4e2fc9081c5eb16f53e8 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sun, 4 Jul 2021 15:03:30 -0700
Subject: support avx512 registers >=16

---
 src/shared/evex.in | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src/shared')

diff --git a/src/shared/evex.in b/src/shared/evex.in
index f848808..6446b52 100644
--- a/src/shared/evex.in
+++ b/src/shared/evex.in
@@ -71,6 +71,20 @@ pub(crate) fn read_evex<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
       let (opcode, operand_code) = table[entry].1[index_lower];
       instruction.opcode = opcode;
       read_evex_operands(words, instruction, operand_code)?;
+      if instruction.prefixes.evex_unchecked().rp() {
+        instruction.regs[0].num |= 0b10000;
+        if ![RegisterBank::X, RegisterBank::Y, RegisterBank::Z].contains(&instruction.regs[0].bank) {
+          return Err(DecodeError::InvalidOperand);
+        }
+      }
+      if instruction.prefixes.evex_unchecked().vex().x() {
+        if instruction.operands.contains(&OperandSpec::RegMMM) {
+          instruction.regs[1].num |= 0b10000;
+          if ![RegisterBank::X, RegisterBank::Y, RegisterBank::Z].contains(&instruction.regs[1].bank) {
+            return Err(DecodeError::InvalidOperand);
+          }
+        }
+      }
       if instruction.prefixes.evex_unchecked().vex().compressed_disp() {
         let overridden_size = match instruction.opcode {
           Opcode::VPEXPANDB => Some(1),
-- 
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