From 003183a4ce31cfb718f4e4083d32c845352c2321 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Fri, 15 Dec 2023 17:26:59 -0800
Subject: more RegSpec constructor validation, fix bug in x86_64 1b reg specs

* the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be
  constructed in two ways that produce "identical" `RegSpec` that are..
  not.
  e.g. `RegSpec::al() != Regspec::rb(0)` even though
  `RegSpec::al().name() == RegSpec::rb(0).name()`.

  this corrects the `rb` constructor at least, but instructions like
  `4830c0` and `30c0` still produce incompatible versions of `al`.

* also fix register numbering used explicit qword-sized RegSpec
  constructors, r12 and r13 used to produce r8 and r9
---
 src/long_mode/mod.rs | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 5132973..7f9719c 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -236,9 +236,15 @@ impl RegSpec {
             panic!("invalid x86 rex-byte reg {}", num);
         }
 
+        let bank = if num < 4 {
+            RegisterBank::B
+        } else {
+            RegisterBank::rB
+        };
+
         RegSpec {
             num,
-            bank: RegisterBank::rB
+            bank,
         }
     }
 
@@ -283,7 +289,7 @@ impl RegSpec {
         rax => 0, rcx => 1, rdx => 2, rbx => 3,
         rsp => 4, rbp => 5, rsi => 6, rdi => 7,
         r8 => 8, r9 => 9, r10 => 10, r11 => 11,
-        r12 => 8, r13 => 9, r14 => 14, r15 => 15
+        r12 => 12, r13 => 13, r14 => 14, r15 => 15
     );
 
     register!(D,
-- 
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