From 20d3219cf05b9ba30dc5a336d735af07f054e4cb Mon Sep 17 00:00:00 2001 From: iximeow Date: Thu, 21 Apr 2022 02:27:38 -0700 Subject: replace size lookup logic with a LUT the match compiled into some indirect branch awfulness!! no thank you --- src/long_mode/mod.rs | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index b4f296e..76f9d93 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -6061,13 +6061,18 @@ fn read_M< #[inline] fn width_to_gp_reg_bank(width: u8, rex: bool) -> RegisterBank { - match width { - 1 => return if rex { RegisterBank::rB } else { RegisterBank::B }, - 2 => return RegisterBank::W, - 4 => return RegisterBank::D, - 8 => return RegisterBank::Q, - _ => unsafe { unreachable_unchecked(); } - } + // transform (width, rex) into an index into an index into a LUT, instead of branching as + // `match` would. + let index = (width.trailing_zeros() << 1) | (rex as u32); + + const BANK_LUT: [RegisterBank; 8] = [ + RegisterBank::B, RegisterBank::rB, + RegisterBank::W, RegisterBank::W, + RegisterBank::D, RegisterBank::D, + RegisterBank::Q, RegisterBank::Q, + ]; + + *BANK_LUT.get(index as usize).unwrap_or_else(|| unsafe { unreachable_unchecked() }) } fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { -- cgit v1.1