From 22baa577c5ba34bc4e89b7019f2666ff7cee4b07 Mon Sep 17 00:00:00 2001 From: iximeow Date: Sun, 21 Mar 2021 03:19:51 -0700 Subject: add tsxldtrk does intel know no bounds --- src/long_mode/display.rs | 6 ++++++ src/long_mode/mod.rs | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) (limited to 'src') diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs index 997a9a9..8750cc6 100644 --- a/src/long_mode/display.rs +++ b/src/long_mode/display.rs @@ -1311,6 +1311,10 @@ const MNEMONICS: &[&'static str] = &[ "clui", "stui", "senduipi", + + // TSXLDTRK + "xsusldtrk", + "xresldtrk", ]; impl Opcode { @@ -2321,6 +2325,8 @@ impl > Colorize { write!(out, "{}", colors.platform_op(self)) } Opcode::CRC32 | diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 6a85542..2c4ac92 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -1966,6 +1966,10 @@ pub enum Opcode { CLUI, STUI, SENDUIPI, + + // TSXLDTRK + XSUSLDTRK, + XRESLDTRK, } #[derive(Debug)] @@ -8326,6 +8330,12 @@ fn unlikely_operands>(decoder: &InstDecoder, mut bytes_iter let m = modrm & 7; match m { 0b000 => { + if instruction.prefixes.repnz() { + instruction.opcode = Opcode::XSUSLDTRK; + instruction.operands[0] = OperandSpec::Nothing; + instruction.operand_count = 0; + return Ok(()); + } if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } @@ -8333,6 +8343,15 @@ fn unlikely_operands>(decoder: &InstDecoder, mut bytes_iter instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } + 0b001 => { + if instruction.prefixes.repnz() { + instruction.opcode = Opcode::XRESLDTRK; + instruction.operands[0] = OperandSpec::Nothing; + instruction.operand_count = 0; + return Ok(()); + } + return Err(DecodeError::InvalidOpcode); + } 0b010 => { if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); -- cgit v1.1