From 5f1d1d7123ae613d5a18ca29247e81781568ca0e Mon Sep 17 00:00:00 2001 From: iximeow Date: Sat, 20 Jul 2019 10:21:22 -0700 Subject: begone, warnings --- src/display.rs | 2 -- src/lib.rs | 35 +++++++++-------------------------- 2 files changed, 9 insertions(+), 28 deletions(-) (limited to 'src') diff --git a/src/display.rs b/src/display.rs index cbf3e61..9d4bc9f 100644 --- a/src/display.rs +++ b/src/display.rs @@ -289,7 +289,6 @@ impl fmt::Display for Opcode { &Opcode::ENTER => write!(f, "{}", "enter"), &Opcode::LEAVE => write!(f, "{}", "leave"), &Opcode::MOV => write!(f, "{}", "mov"), - &Opcode::MOVSD => write!(f, "{}", "movsd"), &Opcode::RETURN => write!(f, "{}", "ret"), &Opcode::PUSHF => write!(f, "{}", "pushf"), &Opcode::WAIT => write!(f, "{}", "wait"), @@ -489,7 +488,6 @@ impl Colorize for Opcode { Opcode::MOVDDUP | Opcode::MOVSLDUP | Opcode::MOV | - Opcode::MOVSD | Opcode::CBW | Opcode::CDW | Opcode::LODS | diff --git a/src/lib.rs b/src/lib.rs index ca86006..288aaae 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -146,6 +146,7 @@ impl RegSpec { } #[allow(non_camel_case_types)] +#[allow(dead_code)] enum SizeCode { b, vd, @@ -762,7 +763,7 @@ const BITWISE_OPCODE_MAP: [Opcode; 8] = [ Opcode::SAL, Opcode::SAR ]; -fn read_opcode_660f_map>(bytes_iter: &mut T, instruction: &mut Instruction, prefixes: Prefixes, length: &mut u8) -> Result { +fn read_opcode_660f_map>(_bytes_iter: &mut T, _instruction: &mut Instruction, _prefixes: Prefixes, _length: &mut u8) -> Result { Err("660f opcode map unsupported".to_string()) } fn read_opcode_f20f_map>(bytes_iter: &mut T, instruction: &mut Instruction, prefixes: Prefixes, length: &mut u8) -> Result { @@ -1952,11 +1953,13 @@ fn read_opcode>(bytes_iter: &mut T, instruction: &mut Instr fn read_E>(bytes_iter: &mut T, prefixes: &Prefixes, m: u8, modbits: u8, width: u8, result: &mut Operand, length: &mut u8) -> Result<(), String> { read_E_anybank(bytes_iter, prefixes, m, modbits, width, result, length, width_to_gp_reg_bank(width, prefixes.rex().present())) } +#[allow(non_snake_case)] fn read_E_xmm>(bytes_iter: &mut T, prefixes: &Prefixes, m: u8, modbits: u8, width: u8, result: &mut Operand, length: &mut u8) -> Result<(), String> { read_E_anybank(bytes_iter, prefixes, m, modbits, width, result, length, RegisterBank::X) } -fn read_E_anybank>(bytes_iter: &mut T, prefixes: &Prefixes, m: u8, modbits: u8, width: u8, result: &mut Operand, length: &mut u8, reg_bank: RegisterBank) -> Result<(), String> { +#[allow(non_snake_case)] +fn read_E_anybank>(bytes_iter: &mut T, prefixes: &Prefixes, m: u8, modbits: u8, _width: u8, result: &mut Operand, length: &mut u8, reg_bank: RegisterBank) -> Result<(), String> { let addr_width = if prefixes.address_size() { 4 } else { 8 }; if modbits == 0b11 { *result = Operand::Register(RegSpec::from_parts(m, prefixes.rex().b(), reg_bank)) @@ -2153,7 +2156,7 @@ fn read_operands>( read_E(bytes_iter, &instruction.prefixes, m, mod_bits, opwidth, &mut instruction.operands[0], length) }, OperandCode::AL_Ob => { - let addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; + let _addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; // stupid RCT thing: let addr_width = if instruction.prefixes.address_size() { 2 } else { 4 }; let opwidth = 1; @@ -2169,7 +2172,7 @@ fn read_operands>( Ok(()) } OperandCode::AX_Ov => { - let addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; + let _addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; // stupid RCT thing: let addr_width = if instruction.prefixes.address_size() { 2 } else { 4 }; let opwidth = imm_width_from_prefixes_64(SizeCode::vqp, &instruction.prefixes); @@ -2185,7 +2188,7 @@ fn read_operands>( Ok(()) } OperandCode::Ob_AL => { - let addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; + let _addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; // stupid RCT thing: let addr_width = if instruction.prefixes.address_size() { 2 } else { 4 }; let opwidth = 1; @@ -2201,7 +2204,7 @@ fn read_operands>( Ok(()) } OperandCode::Ov_AX => { - let addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; + let _addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; // stupid RCT thing: let addr_width = if instruction.prefixes.address_size() { 2 } else { 4 }; let opwidth = imm_width_from_prefixes_64(SizeCode::vqp, &instruction.prefixes); @@ -2796,26 +2799,6 @@ fn read_operands>( Err(reason) => Err(reason) } }, - OperandCode::G_E_xmm => { - let opwidth = 8; - // TODO: ... - let modrm = match bytes_iter.next() { - Some(b) => b, - None => return Err("Out of bytes".to_string()) - }; - *length += 1; - let (mod_bits, r, m) = octets_of(modrm); - -// println!("mod_bits: {:2b}, r: {:3b}, m: {:3b}", mod_bits, r, m); - match read_E_xmm(bytes_iter, &instruction.prefixes, m, mod_bits, opwidth, &mut instruction.operands[1], length) { - Ok(()) => { - instruction.operands[0] = - Operand::Register(RegSpec::from_parts(r, instruction.prefixes.rex().r(), RegisterBank::X)); - Ok(()) - }, - Err(reason) => Err(reason) - } - }, OperandCode::Zv_Ivq(opcode_byte) => { let opwidth = imm_width_from_prefixes_64(SizeCode::vqp, &instruction.prefixes); let reg_idx = opcode_byte & 0x7; -- cgit v1.1