From f6c153d4cf511d05d8f1df21190b73d62c2412bb Mon Sep 17 00:00:00 2001 From: iximeow Date: Sun, 26 Jul 2020 04:20:35 -0700 Subject: bitwise ops, test cases, btr --- src/long_mode/mod.rs | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 1b80b11..fe490e8 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -5492,12 +5492,16 @@ fn read_operands>(decoder: &InstDecoder, mut bytes_iter: T, op @ OperandCode::ModRM_0xc1_Ev_Ib | op @ OperandCode::ModRM_0xd0_Eb_1 | op @ OperandCode::ModRM_0xd1_Ev_1 | + op @ OperandCode::ModRM_0xd2_Eb_CL | op @ OperandCode::ModRM_0xd3_Ev_CL => { instruction.operands[0] = mem_oper; instruction.opcode = BITWISE_OPCODE_MAP[((modrm >> 3) & 7) as usize].clone(); if let OperandCode::ModRM_0xd3_Ev_CL = op { instruction.modrm_rrr = RegSpec::cl(); instruction.operands[1] = OperandSpec::RegRRR; + } else if let OperandCode::ModRM_0xd2_Eb_CL = op { + instruction.modrm_rrr = RegSpec::cl(); + instruction.operands[1] = OperandSpec::RegRRR; } else { let num = match op { OperandCode::ModRM_0xc0_Eb_Ib | -- cgit v1.1