From a781322552d9fb52b7b5e51641f49f12678f682f Mon Sep 17 00:00:00 2001 From: iximeow Date: Thu, 1 Jul 2021 23:54:06 -0700 Subject: reallocate OperandCode, convert disparate registers to array also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode. --- test/long_mode/operand.rs | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'test/long_mode/operand.rs') diff --git a/test/long_mode/operand.rs b/test/long_mode/operand.rs index f0300d6..77ce256 100644 --- a/test/long_mode/operand.rs +++ b/test/long_mode/operand.rs @@ -2,15 +2,15 @@ use yaxpeax_x86::long_mode::{Operand, RegSpec}; #[test] fn register_widths() { - assert_eq!(Operand::Register(RegSpec::rsp()).width(), 8); - assert_eq!(Operand::Register(RegSpec::esp()).width(), 4); - assert_eq!(Operand::Register(RegSpec::sp()).width(), 2); - assert_eq!(Operand::Register(RegSpec::cl()).width(), 1); - assert_eq!(Operand::Register(RegSpec::ch()).width(), 1); - assert_eq!(Operand::Register(RegSpec::gs()).width(), 2); + assert_eq!(Operand::Register(RegSpec::rsp()).width(), Some(8)); + assert_eq!(Operand::Register(RegSpec::esp()).width(), Some(4)); + assert_eq!(Operand::Register(RegSpec::sp()).width(), Some(2)); + assert_eq!(Operand::Register(RegSpec::cl()).width(), Some(1)); + assert_eq!(Operand::Register(RegSpec::ch()).width(), Some(1)); + assert_eq!(Operand::Register(RegSpec::gs()).width(), Some(2)); } #[test] fn memory_widths() { - assert_eq!(Operand::RegDeref(RegSpec::rsp()).width(), 8); + assert_eq!(Operand::RegDeref(RegSpec::rsp()).width(), None); } -- cgit v1.1