From 08eed360fea81ab9328fd0859b813ee01937b5b1 Mon Sep 17 00:00:00 2001 From: iximeow Date: Fri, 16 Aug 2024 21:21:16 -0700 Subject: expand isa feature selection to more bits this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory --- test/long_mode/regspec.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'test/long_mode/regspec.rs') diff --git a/test/long_mode/regspec.rs b/test/long_mode/regspec.rs index 220435f..81416ff 100644 --- a/test/long_mode/regspec.rs +++ b/test/long_mode/regspec.rs @@ -11,7 +11,7 @@ fn test_hash() { let _: HashMap = HashMap::new(); } -#[cfg(features="fmt")] +#[cfg(feature="fmt")] #[test] fn test_labels() { assert_eq!(RegSpec::rip().name(), "rip"); @@ -22,7 +22,7 @@ fn test_labels() { assert_eq!(RegSpec::al().name(), "al"); } -#[cfg(features="fmt")] +#[cfg(feature="fmt")] #[test] fn test_bank_names() { assert_eq!(RegSpec::al().class().name(), "byte"); -- cgit v1.1