From a0fd5a24cb0aa0b697f680c451d928cefe8323b4 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Thu, 21 May 2020 23:09:39 -0700
Subject: add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensions

also add builders to get decoders appropriate for specific
microarchitectures from intel and amd
* low-power architectures are not yet present
---
 test/protected_mode/mod.rs | 64 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

(limited to 'test/protected_mode/mod.rs')

diff --git a/test/protected_mode/mod.rs b/test/protected_mode/mod.rs
index ab3cdc8..9fc603d 100644
--- a/test/protected_mode/mod.rs
+++ b/test/protected_mode/mod.rs
@@ -1035,3 +1035,67 @@ fn only_32bit() {
     test_display(&[0x67, 0xa1, 0xc0, 0xb0], "mov eax, [0xb0c0]");
     test_display(&[0x66, 0x67, 0xa1, 0xc0, 0xb0], "mov ax, [0xb0c0]");
 }
+
+#[test]
+fn test_adx() {
+    test_display(&[0x66, 0x0f, 0x38, 0xf6, 0xc1], "adcx eax, ecx");
+    test_display(&[0x66, 0x0f, 0x38, 0xf6, 0x01], "adcx eax, [ecx]");
+    test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0xc1], "adox eax, ecx");
+    test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0x01], "adox eax, [ecx]");
+}
+
+#[test]
+fn test_prefetchw() {
+    test_display(&[0x0f, 0x0d, 0x08], "prefetchw [eax]");
+}
+
+#[test]
+fn test_lzcnt() {
+    test_display(&[0x66, 0xf3, 0x0f, 0xbd, 0xc1], "lzcnt ax, cx");
+    test_display(&[0xf3, 0x0f, 0xbd, 0xc1], "lzcnt eax, ecx");
+}
+
+#[test]
+fn test_svm() {
+    test_display(&[0x0f, 0x01, 0xdf], "invlpga eax, ecx");
+    test_display(&[0x0f, 0x01, 0xde], "skinit eax");
+    test_display(&[0x0f, 0x01, 0xdd], "clgi");
+    test_display(&[0x0f, 0x01, 0xdc], "stgi");
+    test_display(&[0x0f, 0x01, 0xdb], "vmsave eax");
+    test_display(&[0x0f, 0x01, 0xda], "vmload eax");
+    test_display(&[0x0f, 0x01, 0xd9], "vmmcall");
+    test_display(&[0x0f, 0x01, 0xd8], "vmrun eax");
+}
+
+#[test]
+fn test_movbe() {
+    test_display(&[0x0f, 0x38, 0xf0, 0x06], "movbe eax, [esi]");
+}
+
+#[test]
+fn test_tsx() {
+    test_display(&[0xc6, 0xf8, 0x10], "xabort 0x10");
+    test_display(&[0xc7, 0xf8, 0x10, 0x12, 0x34, 0x56, 0x78], "xbegin 0x78563412");
+    test_display(&[0x66, 0xc7, 0xf8, 0x10, 0x12, 0x34], "xbegin 0x3412");
+    test_display(&[0x0f, 0x01, 0xd5], "xend");
+    test_display(&[0x0f, 0x01, 0xd6], "xtest");
+}
+
+#[test]
+fn test_rand() {
+    test_display(&[0x0f, 0xc7, 0xfd], "rdseed ebp");
+    test_display(&[0x66, 0x0f, 0xc7, 0xfd], "rdseed bp");
+    test_display(&[0x0f, 0xc7, 0xf5], "rdrand ebp");
+    test_display(&[0x66, 0x0f, 0xc7, 0xf5], "rdrand bp");
+}
+
+#[test]
+fn test_sha() {
+    test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0x40], "sha1rnds4 xmm2, [edx], 0x40");
+    test_display(&[0x0f, 0x38, 0xc8, 0x12], "sha1nexte xmm2, [edx]");
+    test_display(&[0x0f, 0x38, 0xc9, 0x12], "sha1msg1 xmm2, [edx]");
+    test_display(&[0x0f, 0x38, 0xca, 0x12], "sha1msg2 xmm2, [edx]");
+    test_display(&[0x0f, 0x38, 0xcb, 0x12], "sha256rnds2 xmm2, [edx]");
+    test_display(&[0x0f, 0x38, 0xcc, 0x12], "sha256msg1 xmm2, [edx]");
+    test_display(&[0x0f, 0x38, 0xcd, 0x12], "sha256msg2 xmm2, [edx]");
+}
-- 
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