From a0fd5a24cb0aa0b697f680c451d928cefe8323b4 Mon Sep 17 00:00:00 2001 From: iximeow Date: Thu, 21 May 2020 23:09:39 -0700 Subject: add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensions also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present --- test/protected_mode/operand.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'test/protected_mode/operand.rs') diff --git a/test/protected_mode/operand.rs b/test/protected_mode/operand.rs index 08a24be..8fda181 100644 --- a/test/protected_mode/operand.rs +++ b/test/protected_mode/operand.rs @@ -1,5 +1,5 @@ use yaxpeax_arch::{Decoder, LengthedInstruction}; -use yaxpeax_x86::long_mode::{DecodeError, InstDecoder, Opcode}; +use yaxpeax_x86::protected_mode::{DecodeError, InstDecoder, Opcode, Operand, RegSpec}; #[test] fn register_widths() { @@ -12,5 +12,5 @@ fn register_widths() { #[test] fn memory_widths() { - assert_eq!(Operand::RegDeref(RegSpec::rsp()).width(), 4); + assert_eq!(Operand::RegDeref(RegSpec::esp()).width(), 4); } -- cgit v1.1