From 4e61dc5e3ea882022e815814ed324fa7515923a6 Mon Sep 17 00:00:00 2001
From: iximeow <me@iximeow.net>
Date: Sun, 9 Aug 2020 02:07:52 -0700
Subject: support four-reg operand forms, new tests
---
test/long_mode/mod.rs | 9 +++++++++
1 file changed, 9 insertions(+)
(limited to 'test')
diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs
index bd5008c..c56c732 100644
--- a/test/long_mode/mod.rs
+++ b/test/long_mode/mod.rs
@@ -1394,6 +1394,15 @@ fn test_vex() {
test_instr(&[0xc5, 0xfd, 0xee, 0xd9], "vpmaxsw ymm3, ymm0, ymm1");
test_instr(&[0xc4, 0xe3, 0x7d, 0x19, 0xd1, 0x01], "vextractf128 xmm1, ymm2, 0x1");
test_instr(&[0xc4, 0xc3, 0x75, 0x38, 0x7c, 0x12, 0x05, 0x01], "vinserti128 ymm7, ymm1, [r10 + rdx * 1 + 0x5], 0x1");
+ test_instr(&[0xc4, 0xc3, 0x75, 0x42, 0x7c, 0x12, 0x05, 0x61], "vmpsadbw ymm7, ymm1, [r10 + rdx * 1 + 0x5], 0x61");
+ test_instr(&[0xc4, 0xc3, 0x75, 0x46, 0x7c, 0x12, 0x05, 0x61], "vperm2i128 ymm7, ymm1, [r10 + rdx * 1 + 0x5], 0x61");
+ test_instr(&[0xc4, 0xc3, 0x75, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps ymm7, ymm1, [r10 + rdx * 1 + 0x5], ymm6");
+ test_instr(&[0xc4, 0xc3, 0x71, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps xmm7, xmm1, [r10 + rdx * 1 + 0x5], xmm6");
+ test_instr(&[0xc4, 0xc3, 0x71, 0x4a, 0xcc, 0x61], "vblendvps xmm7, xmm1, xmm12, xmm6");
+ test_instr(&[0xc4, 0xc3, 0x75, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd ymm7, ymm1, [r10 + rdx * 1 + 0x5], ymm6");
+ test_instr(&[0xc4, 0xc3, 0x71, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd xmm7, xmm1, [r10 + rdx * 1 + 0x5], xmm6");
+ test_instr(&[0xc4, 0xc3, 0x71, 0x4b, 0xcc, 0x61], "vblendvpd xmm7, xmm1, xmm12, xmm6");
+ test_instr(&[0xc4, 0xc3, 0x71, 0x4c, 0x7c, 0x12, 0x05, 0x61], "vpblendvb xmm7, xmm1, [r10 + rdx * 1 + 0x5], xmm6");
}
#[test]
--
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