diff options
author | iximeow <me@iximeow.net> | 2025-03-19 19:15:52 -0700 |
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committer | iximeow <me@iximeow.net> | 2025-03-19 19:15:52 -0700 |
commit | 8e73e3eacaab4db14d32439fef4e7be13c973715 (patch) | |
tree | ad4551064cad63cb31e749ecbe3dece167d3f9a4 /src | |
parent | 3dca3441fd3a21290eb2920b3d8c03cb9ea241f8 (diff) |
moderate progress...
Diffstat (limited to 'src')
-rw-r--r-- | src/display.rs | 7 | ||||
-rw-r--r-- | src/lib.rs | 32 |
2 files changed, 39 insertions, 0 deletions
diff --git a/src/display.rs b/src/display.rs index 46fd534..11d5489 100644 --- a/src/display.rs +++ b/src/display.rs @@ -244,6 +244,13 @@ impl fmt::Display for Opcode { Opcode::StoreMemw => { f.write_str("memw") }, Opcode::StoreMemd => { f.write_str("memd") }, + Opcode::MembAdd => { f.write_str("memb") }, + Opcode::MembSub => { f.write_str("memb") }, + Opcode::MembAnd => { f.write_str("memb") }, + Opcode::MembOr => { f.write_str("memb") }, + Opcode::MembClr => { f.write_str("memb") }, + Opcode::MembSet => { f.write_str("memb") }, + Opcode::Membh => { f.write_str("membh") }, Opcode::MemhFifo => { f.write_str("memh_fifo") }, Opcode::Memubh => { f.write_str("memubh") }, @@ -1636,7 +1636,39 @@ fn decode_instruction< // 0b11, so bits are like 0011|11xxxx // these are all stores to Rs+#u6:N, shift is determined by op size. // the first few are stores of immediates, most others operate on registers. + let opc_bits = (inst >> 21) & 0b11111; + let opc_upper = opc_bits >> 3; + let opc_lower = opc_bits & 0b11; + let uuuuuu = (inst >> 7) & 0b111111; + + match opc_upper { + 0b00 | + 0b01 => { + let i7 = inst & 0b111_1111; + let i_hi = ((inst >> 13) & 0b1) << 7; + let i = i_hi | i7; + + (match opc_upper { + 0b00 => { + handler.on_opcode_decoded(Opcode::StoreMemb)?; + } + 0b01 => { + Ok(Opcode::StoreMemh), + } + 0b10 => { + Ok(Opcode::StoreMemd), + } + _ => Err(DecodeError::InvalidOpcode) + }?)?; + handler.on_source_decoded(Operand::imm_i8(i as i8))?; + }, + 0b10 => { + + }, + _ => { panic!("TODO: other: {}", other); + } + } } } } |