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Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 37 |
1 files changed, 32 insertions, 5 deletions
@@ -3,7 +3,33 @@ [](https://crates.io/crates/yaxpeax-hexagon) [](https://docs.rs/yaxpeax-hexagon) -qualcomm hexagon decoder implemented as part of the yaxpeax project, implementing traits provided by `yaxpeax-arch`. +Qualcomm Hexagon decoder implemented as part of the yaxpeax project, implementing traits provided by `yaxpeax-arch`. + +support is good enough to make sense of many programs, but not complete: + +- [x] instructions mentioned in the V62 and V73 manuals. +- [x] system instructions documented in V62 and earlier +- [ ] undocumented system instructions in V73 and later +- [ ] HVX (in any version) +- [ ] duplex instructions + +between V67 and V73, Qualcomm decided to remove most mentions of the Hexagon +supervisor mode from their manuals. the LLVM target has had support for these +instructions since late 2023, so LLVM-derived disassemblers should support +them. it is not immediately clear to me that system instructions have the same +encodings or semantic on later architectures - i largely lack programs known to +target newer versions to validate that disassembly still looks reasonable. + +Hexagon in real use seems to rely on a hypervisor (probably +Qualcomm-maintained? similar to their +[minivm](https://github.com/quic/hexagonMVM)?) which system instructions are +intended to support, then "User" and "Guest" modes which are more openly +documented in public manuals. none the less, `hexagonMVM` uses these +now-undocumented system instructions [for system register +management](https://github.com/quic/hexagonMVM/blob/db795a9/minivm.S#L259), TLB +management later on, traps, and so on. these system instructions are also +important to process to make sense of the entrypoints of in-the-wild Hexagon +firmware images. ### features @@ -18,13 +44,14 @@ the canonical copy of `yaxpeax-hexagon` is at [https://git.iximeow.net/yaxpeax-h ### see also -* [idp\_hexagon](https://github.com/n-o-o-n/idp_hexagon): IDA pro module for hexagon. heavily derived from LLVM. +* [idp\_hexagon](https://github.com/n-o-o-n/idp_hexagon): IDA pro module for Hexagon. heavily derived from LLVM. * [llvm](https://github.com/llvm/llvm-project/tree/e03f427/llvm/lib/Target/Hexagon) -* [r2hexagon](https://github.com/radareorg/r2hexagon): radare2's hexagon disassembler. generated from manuals. -* [hexag00n](https://github.com/programa-stic/hexag00n): python-based hexagon disassembler with IDA plugin +* [r2hexagon](https://github.com/radareorg/r2hexagon): radare2's Hexagon disassembler. generated from manuals. +* [hexag00n](https://github.com/programa-stic/hexag00n): python-based Hexagon disassembler with IDA plugin * [hexagon](https://github.com/gsmk/hexagon): another IDA pro processor module. wrapper for Sourcery CodeBench. * [nogaxeh](https://github.com/ANSSI-FR/nogaxeh): another IDA pro processor module -* [rz-hexagon](https://github.com/rizinorg/rz-hexagon): hexagon disassembler for rizin. generated from LLVM. +* [rz-hexagon](https://github.com/rizinorg/rz-hexagon): Hexagon disassembler for rizin. generated from LLVM. ### changelog + a changelog across crate versions is maintained in the `CHANGELOG` file located in the repo, as well as [online](https://git.iximeow.net/yaxpeax-hexagon/tree/CHANGELOG). |