diff options
Diffstat (limited to 'src/display.rs')
| -rw-r--r-- | src/display.rs | 87 |
1 files changed, 85 insertions, 2 deletions
diff --git a/src/display.rs b/src/display.rs index 84bc06b..8970a50 100644 --- a/src/display.rs +++ b/src/display.rs @@ -43,6 +43,38 @@ impl fmt::Display for Instruction { // | Rd = not(Rs) | Rd = sub(#-1,Rs) | // | Rd = neg(Rs) | Rd = sub(#0,Rs) | // | Rdd = Rss | Rdd = combine(Rss.H32, Rss.L32) | + + // stores put the mnemonic on LHS + static STORES: &[Opcode] = &[ + Opcode::StoreMemb, Opcode::StoreMemh, Opcode::StoreMemw, Opcode::StoreMemd + ]; + if STORES.contains(&self.opcode) { + write!(f, "{}({}) = {}", + self.opcode, self.dest.expect("TODO: unreachable; store has a destination"), + self.sources[0] + )?; + return Ok(()); + } + + static JUMPS: &[Opcode] = &[ + Opcode::JumpEq, Opcode::JumpNeq, Opcode::JumpGt, Opcode::JumpLe, + Opcode::JumpGtu, Opcode::JumpLeu, Opcode::JumpBitSet, Opcode::JumpBitClear, + ]; + if JUMPS.contains(&self.opcode) { + use crate::BranchHint; + let hint_label = match self.branch_hinted.unwrap() { + BranchHint::Taken => { "t" }, + BranchHint::NotTaken => { "nt" }, + }; + write!(f, "if ({}({}, {})) jump:{} {}", + self.opcode.cmp_str().unwrap(), // TODO: unwrap_unchecked?? + self.sources[0], + self.sources[1], + hint_label, + self.dest.unwrap(), + )?; + return Ok(()); + } if let Some(o) = self.dest.as_ref() { write!(f, "{} = ", o)?; } @@ -77,12 +109,26 @@ impl fmt::Display for Opcode { Opcode::BUG => { f.write_str("BUG") }, Opcode::Nop => { f.write_str("nop") }, Opcode::Jump => { f.write_str("jump") }, + Opcode::Call => { f.write_str("call") }, Opcode::Memb => { f.write_str("memb") }, Opcode::Memub => { f.write_str("memub") }, Opcode::Memh => { f.write_str("memh") }, Opcode::Memuh => { f.write_str("memuh") }, Opcode::Memw => { f.write_str("memw") }, Opcode::Memd => { f.write_str("memd") }, + + Opcode::LoadMemb => { f.write_str("memb") }, + Opcode::LoadMemub => { f.write_str("memub") }, + Opcode::LoadMemh => { f.write_str("memh") }, + Opcode::LoadMemuh => { f.write_str("memuh") }, + Opcode::LoadMemw => { f.write_str("memw") }, + Opcode::LoadMemd => { f.write_str("memd") }, + + Opcode::StoreMemb => { f.write_str("memb") }, + Opcode::StoreMemh => { f.write_str("memh") }, + Opcode::StoreMemw => { f.write_str("memw") }, + Opcode::StoreMemd => { f.write_str("memd") }, + Opcode::Membh => { f.write_str("membh") }, Opcode::MemhFifo => { f.write_str("memh_fifo") }, Opcode::Memubh => { f.write_str("memubh") }, @@ -105,6 +151,22 @@ impl fmt::Display for Opcode { Opcode::And => { f.write_str("and") }, Opcode::Sub => { f.write_str("sub") }, Opcode::Or => { f.write_str("or") }, + + Opcode::JumpEq => { f.write_str("cmp.eq+jump") }, + Opcode::JumpNeq => { f.write_str("cmp.neq+jump") }, + Opcode::JumpGt => { f.write_str("cmp.gt+jump") }, + Opcode::JumpLe => { f.write_str("cmp.le+jump") }, + Opcode::JumpGtu => { f.write_str("cmp.gtu+jump") }, + Opcode::JumpLeu => { f.write_str("cmp.leu+jump") }, + Opcode::JumpBitSet => { f.write_str("tstbit+jump") }, + Opcode::JumpBitClear => { f.write_str("!tstbit+jump") }, + + Opcode::Tlbw => { f.write_str("tlbw") }, + Opcode::Tlbr => { f.write_str("tlbr") }, + Opcode::Tlbp => { f.write_str("tlbp") }, + Opcode::TlbInvAsid => { f.write_str("tlbinvasid") }, + Opcode::Ctlbw => { f.write_str("ctlbw") }, + Opcode::Tlboc => { f.write_str("tlboc") }, } } } @@ -116,11 +178,20 @@ impl fmt::Display for Operand { f.write_str("BUG (operand)") } Operand::PCRel32 { rel } => { - f.write_str("idk!") + write!(f, "#{}", rel) } Operand::Gpr { reg } => { write!(f, "R{}", reg) } + Operand::Cr { reg } => { + write!(f, "C{}", reg) + } + Operand::Sr { reg } => { + write!(f, "S{}", reg) + } + Operand::GprNew { reg } => { + write!(f, "R{}.new", reg) + } Operand::GprLow { reg } => { write!(f, "R{}.L", reg) } @@ -130,6 +201,12 @@ impl fmt::Display for Operand { Operand::Gpr64b { reg_low } => { write!(f, "R{}:{}", reg_low + 1, reg_low) } + Operand::Cr64b { reg_low } => { + write!(f, "C{}:{}", reg_low + 1, reg_low) + } + Operand::Sr64b { reg_low } => { + write!(f, "S{}:{}", reg_low + 1, reg_low) + } Operand::PredicateReg { reg } => { write!(f, "P{}", reg) } @@ -137,7 +214,7 @@ impl fmt::Display for Operand { write!(f, "R{}+#{}", base, offset) } Operand::RegShiftedReg { base, index, shift } => { - write!(f, "R{} + R{} << {}", base, index, shift) + write!(f, "R{} + R{}<<{}", base, index, shift) } Operand::ImmU8 { imm } => { write!(f, "#0x{:x}", imm) @@ -151,6 +228,12 @@ impl fmt::Display for Operand { Operand::ImmI16 { imm } => { write!(f, "#{:}", imm) } + Operand::ImmI32 { imm } => { + write!(f, "#{:}", imm) + } + Operand::ImmU32 { imm } => { + write!(f, "#{:}", imm) + } } } } |