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6 daysanother fuzz victory!iximeow
6 daysfuzz cases: only 64 system registers, display should never paniciximeow
6 daysseeming goodiximeow
6 dayscleanupiximeow
6 daysthe rest of duplexes, oopsiximeow
6 daysl2 cache management instructions are system and undocumentediximeow
6 daysduplex instructions seem to kind of workiximeow
7 daysshift plus extenders no longer ambiguousiximeow
7 daysthe rest of the extendersiximeow
7 dayspredicated store was RegOffset when it should be RegOffsetInciximeow
and a few more extender tests
7 daysjust... decoded predicated loads wrong...iximeow
7 daysmore instruction extendersiximeow
7 daysinitial list of extendable instructions, fix memub/memuh decode errorsiximeow
8 daysinitial instruction extender support, more system instructionsiximeow
8 daysmore registers as lower case, pc-relative shown like every other archiximeow
10 dayscontrol, gpr register names, readmeiximeow
11 dayssystem control register names, more cleanupiximeow
11 dayssupervisor mode instructions, control register namesiximeow
12 dayswowowowow cargo test passesiximeow
13 daysit is done (not all system, duplex, extender tho)iximeow
13 dayssfrecipa, more test cases, more inst variantsiximeow
13 daysmore test coverage, getting close..iximeow
13 daysmore tests and cleanup; sub, instruction labels, sfmpyiximeow
additionally, AndNot should show its special assign mode if one is set. a few instructions have 64-bit register pairs that can be conjugated. vrmpywoh should have operands. :sat applied incompletely AndNot can have |=, &=, and ^= assign modes, not += had a sub with backwards operands
13 dayswretched architecture which does not know the light of g*diximeow
13 daysmore pmpy, ignore shift_{left,right} with amt=0iximeow
13 daysgross hacks for AddAsl, fix AddMpyi decodingiximeow
13 daysmore test coverage, gpr conjugatesiximeow
14 daysshift vs sat order in display, vxaddsubh/vxsubaddh/extractu/decbiniximeow
14 daysfix extractu/shuff{e,o}{b,h}, add many test cases, handle AddMpyiiximeow
2025-04-05theoretically all non-system instructions...iximeow
2025-03-291101* is all thats left...iximeow
2025-03-280b1000..0b1100: DONE!iximeow
2025-03-23shifts and MORE transcription errors :(iximeow
2025-03-23thats 0110... doneiximeow
2025-03-23more loop support, transcription errors, etciximeow
2025-03-22wow 1001... is done nowiximeow
2025-03-22more loads, fix wrong dest ops for some loads..iximeow
2025-03-22warnings-b-goneiximeow
2025-03-22more tests, support more loads/storesiximeow
2025-03-21assign-merge is recorded now, 0100.. is decodediximeow
2025-03-19moderate progress...iximeow
2024-12-23checkpointiximeow
2024-11-10some iclass 1100, 1010, 1001iximeow
2024-10-08more progressiximeow
2024-10-06more support, docs about some weird instruction shapesiximeow
2024-10-05more ops, transcription errorsiximeow
2024-10-05thank you, warningsiximeow
2024-10-05broader support, maybe 1/8th through. also v73 manual does not list ↵iximeow
supervisor instructions...
2024-09-29starting to look like a disassembleriximeow
2024-09-28sketching things outiximeow
generated by cgit v1.1 at 2025-04-20 10:31:50 +0000