yaxpeax-power - yaxpeax POWER family decoder

Age	Commit message (Collapse)	Author
7 days	mtmsr, cr bit parsing, crclr	iximeow

7 days	wip: displaystyle plumbing	iximeow
	fix an off-by-four in branch offsets
7 days	bclr does not set control register lol	iximeow

7 days	i suppose API items should be public	iximeow

7 days	correctly handle xenia not printing mtocrf	iximeow

7 days	paper over an LMA deficiency for now	iximeow

7 days	mtocrf, srdi, clrldi handling, plus lingering "crf"s	iximeow

7 days	be more willing to print prettied branch mnemonics when hints are present	iximeow

7 days	yet another swing at branch handling...	iximeow

7 days	some immediates are logical (not signed)	iximeow

7 days	trying to get my head around bcctrl again	iximeow

7 days	get more tests in line and correct wonky alias tests	iximeow

7 days	it's xenia that prints the spr number backwards, also untangle mfocrf	iximeow

7 days	clear all instruction state until i've got this more nuanced	iximeow

7 days	vcmpgefp assert, whoops	iximeow

7 days	do not have one-off weird crf register	iximeow

7 days	format this crf the same as any other CrField	iximeow

7 days	slwi alias ;;	iximeow

7 days	accessors for instruction operation bits...	iximeow

7 days	xenia was not exhaustive, now is exhaustiver. fix more issues	iximeow

7 days	omg xenia agrees	iximeow

7 days	parallelize xenia comparison (~5 minutes now?)	iximeow

7 days	bcctr canonicalization taken care of?	iximeow

7 days	mangled or->mr alias handling..	iximeow

7 days	literal display format testing	iximeow

7 days	better (any) bclr normalization, longer tail of xenia comparison	iximeow

7 days	helpers to build register structs	iximeow

7 days	many more xenia mismatches	iximeow
	mostly around vector instructions, but several cases of inappropriately accepting instructions Xenon does not know. and finally answering what in the world a "PowerPC A" is. it's Amazon.
7 days	tests: normalize rldicr into clrrdi correctly	iximeow

7 days	set up operands for more altivec instructions	iximeow
	also tolerate dumpbin-style `01234h` hex offsets
7 days	working through several vector load/stores	iximeow

7 days	library users should be able to get data from operands ig	iximeow

7 days	much faster xenia differential, several debug .. bugs	iximeow

7 days	make some bits of Instruction and related accessible	iximeow
	also set instruction lengths
7 days	handle xenia printing vspltb weird	iximeow

7 days	separate out xenia differential	iximeow
	also fix two issues: * vmaxsp was just a typo. should have been vmaxsb. * mcrf operands are CR fields which have actual operand forms now.
7 days	everything vs xenia is accounted for on the random xex i threw at it	iximeow

7 days	many improvements from and in comparing with xenia	iximeow
	Power ISA branches are.. challenging and varied. support float/double instructions, trap-word-conditional instructions are printed properly, many more fixes
2026-08-08	simplify immediate parsing, test sub aliases properly	iximeow

2026-07-25	mostly works?	iximeow

2026-07-12	very initial	iximeow