yaxpeax-power - yaxpeax POWER family decoder

Age	Commit message (Collapse)	Author
7 days	readme, changelog, etcno-gods-no-	iximeow

7 days	last bits of lining up tests to current impl..	iximeow

7 days	missing docs	iximeow

7 days	support no-fmt builds	iximeow

7 days	a bunch of test utils, goodfile	iximeow

7 days	clean out a few more TODOs that are TODONE	iximeow

7 days	update TODO	iximeow

7 days	use a real yaxpeax-arch	iximeow

7 days	add that back in	iximeow

7 days	unblanket DisplaySinkExt, isel Register-or-Zero	iximeow

7 days	use RegisterOrZero + new MemoryIndexed for indexed memory accesses	iximeow

7 days	xeno's release	iximeow
	fix the gqr panic on 7, operand accessors, clean up a bunch of tests, ppc64le helper for InstDecoder, get derives in better shape, some more docs, fix confusion about when lk/aa bits are set for branches, make `BI` consistently a `CrBit`.
7 days	working through a very long tail of one-off incompatibilities	iximeow

7 days	hrfid, mtrsd(ish), lfdp, legacy svc, fpu	iximeow

7 days	mostly doing dealias now	iximeow

7 days	fpu instructions existed in POWER1 and POWER2 too	iximeow

7 days	big mix of small errors	iximeow

7 days	lfq register confusion	iximeow

7 days	sign extend vspltis* correctly	iximeow

7 days	extra isel row	iximeow

7 days	other small mixups	iximeow

7 days	isel wrong row	iximeow

7 days	POWER2 is not "Power v2.0", some bit twiddling issues	iximeow

7 days	dquaq was off by one	iximeow

7 days	handle immediate signedness better	iximeow

7 days	dquai .te is signed	iximeow

7 days	dfp pair handling issues	iximeow

7 days	that makes a lot more sense: mulo was off by a row..	iximeow

7 days	lwarx, mbar/eieio	iximeow

7 days	ddedpd, denbcdq, related confusion	iximeow

7 days	more transactional, hrfid, isel	iximeow

7 days	transactional v2.07 + dozi operand order	iximeow

7 days	floats, dcbtt should work, stfqx	iximeow

7 days	finally found a citation for old POWER1/POWER2 instructions	iximeow

7 days	docs, ppc64	iximeow
	very stale test expectations display is "less" gross now get more isa rejection for yet-unsupported arches more in place mtsrd operand order, dcbi/dcbt/dcbz
7 days	start covering other later power instructions, maybe	iximeow

7 days	gekko differential, paired singles support	iximeow

7 days	working through differences vs ppcd, mostly ppc64 vs not	iximeow

7 days	preliminary Cell PPU comparison	iximeow

7 days	support altivec/non-power data stream instructions	iximeow

7 days	finish updating to new arch	iximeow

7 days	maybe some of this generic stuff will work out??	iximeow

7 days	misc cleanup, ripping out instruction/operand formatting overrides because ↵	iximeow
	they were unused
7 days	vmx128 is vmx128 only	iximeow

7 days	docs	iximeow

7 days	differential parsing improvements	iximeow

7 days	more test fixes and nonsense cleanup	iximeow

7 days	docs, fix warnings, display no-panic	iximeow

7 days	might be consistently plumbing display rules now..	iximeow

7 days	whacky alias idea	iximeow