diff options
| author | iximeow <me@iximeow.net> | 2021-07-03 14:43:52 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-07-03 14:43:52 -0700 |
| commit | 582c4e44579d4bbb9dcec9d12c23c8b774db3cfb (patch) | |
| tree | 68af64a01cdd16f52ecba79da0aba7d1b4f533ee | |
| parent | 11ce930421ba8b534024f6695dff8fdfd7e47ff0 (diff) | |
do not reject prefixed sgdt, add a TODO for xop
not that xop will ever be wanted, rip
| -rw-r--r-- | src/long_mode/mod.rs | 18 | ||||
| -rw-r--r-- | src/protected_mode/mod.rs | 10 |
2 files changed, 14 insertions, 14 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 9111faa..f8704c0 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -6943,6 +6943,9 @@ fn read_0f38_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { fn read_0f3a_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { if prefixes.rep() { + if prefixes.operand_size() || prefixes.repnz() { + return OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing); + } return match opcode { 0xf0 => OpcodeRecord(Interpretation::Instruction(Opcode::HRESET), OperandCode::ModRM_0xf30f3af0), _ => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -7645,7 +7648,8 @@ fn read_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpe instruction.operands[0] = mem_oper; let r = (modrm >> 3) & 7; if r >= 1 { - return Err(DecodeError::InvalidOpcode); + // TODO: this is where XOP decoding would occur + return Err(DecodeError::IncompleteDecoder); } instruction.opcode = [ Opcode::POP, @@ -9162,13 +9166,13 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; if r == 0 { - if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { - return Err(DecodeError::InvalidOperand); - } - let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { + if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { + return Err(DecodeError::InvalidOperand); + } + instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; match m { @@ -9298,10 +9302,6 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { - if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { - return Err(DecodeError::InvalidOperand); - } - match m { 0b000 => { instruction.opcode = Opcode::VMRUN; diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs index 0497db6..c9ba9f2 100644 --- a/src/protected_mode/mod.rs +++ b/src/protected_mode/mod.rs @@ -6868,6 +6868,9 @@ fn read_0f38_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { fn read_0f3a_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { if prefixes.rep() { + if prefixes.operand_size() || prefixes.repnz() { + return OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing); + } return match opcode { 0xf0 => OpcodeRecord(Interpretation::Instruction(Opcode::HRESET), OperandCode::ModRM_0xf30f3af0), _ => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -7517,7 +7520,8 @@ fn read_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpe instruction.operands[0] = mem_oper; let r = (modrm >> 3) & 7; if r >= 1 { - return Err(DecodeError::InvalidOpcode); + // TODO: this is where XOP decoding would occur + return Err(DecodeError::IncompleteDecoder); } instruction.opcode = [ Opcode::POP, @@ -9119,10 +9123,6 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { - if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { - return Err(DecodeError::InvalidOperand); - } - match m { 0b000 => { instruction.opcode = Opcode::VMRUN; |