extend prefixed opcode support, add tests for alternate opcode maps

3 files changed, 499 insertions, 18 deletions

diff --git a/src/display.rs b/src/display.rs
index a3cd643..7ec7f0f 100644
--- a/src/display.rs
+++ b/src/display.rs
@@ -183,6 +183,24 @@ impl <T: std::fmt::Write> Colorize<T> for Operand {
 impl fmt::Display for Opcode {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         match self {
+            &Opcode::POPCNT => write!(f, "{}", "popcnt"),
+            &Opcode::MOVDQU => write!(f, "{}", "movdqu"),
+            &Opcode::MOVQ => write!(f, "{}", "movq"),
+            &Opcode::CMPSS => write!(f, "{}", "cmpss"),
+            &Opcode::CMPSD => write!(f, "{}", "cmpsd"),
+            &Opcode::UNPCKLPS => write!(f, "{}", "unpcklps"),
+            &Opcode::UNPCKHPS => write!(f, "{}", "unpckhps"),
+            &Opcode::MOVUPS => write!(f, "{}", "movups"),
+            &Opcode::MOVQ2DQ => write!(f, "{}", "movq2dq"),
+            &Opcode::MOVDQ2Q => write!(f, "{}", "movdq2q"),
+            &Opcode::RSQRTSS => write!(f, "{}", "rsqrtss"),
+            &Opcode::MOVSHDUP => write!(f, "{}", "movshdup"),
+            &Opcode::CVTTPS2DQ => write!(f, "{}", "cvttps2dq"),
+            &Opcode::CVTPD2DQ => write!(f, "{}", "cvtpd2dq"),
+            &Opcode::RCPSS => write!(f, "{}", "rcpss"),
+            &Opcode::CVTDQ2PD => write!(f, "{}", "cvtdq2pd"),
+            &Opcode::PSHUFHW => write!(f, "{}", "pshufhw"),
+            &Opcode::PSHUFLW => write!(f, "{}", "pshuflw"),
             &Opcode::XADD => write!(f, "{}", "xadd"),
             &Opcode::BT => write!(f, "{}", "bt"),
             &Opcode::BTS => write!(f, "{}", "bts"),
@@ -329,6 +347,7 @@ impl fmt::Display for Opcode {
             &Opcode::SAR => write!(f, "{}", "sar"),
             &Opcode::SAL => write!(f, "{}", "sal"),
             &Opcode::SHR => write!(f, "{}", "shr"),
+            &Opcode::SHRD => write!(f, "{}", "shrd"),
             &Opcode::SHL => write!(f, "{}", "shl"),
             &Opcode::RCR => write!(f, "{}", "rcr"),
             &Opcode::RCL => write!(f, "{}", "rcl"),
@@ -386,6 +405,8 @@ impl fmt::Display for Opcode {
 impl <T: std::fmt::Write> Colorize<T> for Opcode {
     fn colorize(&self, colors: Option<&ColorSettings>, out: &mut T) -> std::fmt::Result {
         match self {
+            Opcode::RCPSS |
+            Opcode::RSQRTSS |
             Opcode::SQRTSD |
             Opcode::ADDSD |
             Opcode::SUBSD |
@@ -408,6 +429,7 @@ impl <T: std::fmt::Write> Colorize<T> for Opcode {
             Opcode::SAR |
             Opcode::SAL |
             Opcode::SHR |
+            Opcode::SHRD |
             Opcode::SHL |
             Opcode::RCR |
             Opcode::RCL |
@@ -423,6 +445,7 @@ impl <T: std::fmt::Write> Colorize<T> for Opcode {
             Opcode::ADD |
             Opcode::ADC |
             Opcode::SUB |
+            Opcode::POPCNT |
             Opcode::BT |
             Opcode::BTS |
             Opcode::BTR |
@@ -470,6 +493,9 @@ impl <T: std::fmt::Write> Colorize<T> for Opcode {
             /* Data transfer */
             Opcode::MOVSS |
             Opcode::MOVSD |
+            Opcode::CVTDQ2PD |
+            Opcode::CVTPD2DQ |
+            Opcode::CVTTPS2DQ |
             Opcode::CVTSI2SS |
             Opcode::CVTSI2SD |
             Opcode::CVTTSD2SI |
@@ -478,6 +504,10 @@ impl <T: std::fmt::Write> Colorize<T> for Opcode {
             Opcode::CVTTSS2SI |
             Opcode::CVTSS2SI |
             Opcode::CVTSS2SD |
+            Opcode::PSHUFHW |
+            Opcode::PSHUFLW |
+            Opcode::UNPCKHPS |
+            Opcode::UNPCKLPS |
             Opcode::LDDQU |
             Opcode::CLC |
             Opcode::CLI |
@@ -487,6 +517,12 @@ impl <T: std::fmt::Write> Colorize<T> for Opcode {
             Opcode::STD |
             Opcode::MOVDDUP |
             Opcode::MOVSLDUP |
+            Opcode::MOVDQ2Q |
+            Opcode::MOVDQU |
+            Opcode::MOVQ |
+            Opcode::MOVQ2DQ |
+            Opcode::MOVSHDUP |
+            Opcode::MOVUPS |
             Opcode::MOV |
             Opcode::CBW |
             Opcode::CDW |
@@ -544,6 +580,8 @@ impl <T: std::fmt::Write> Colorize<T> for Opcode {
             Opcode::CMPS |
             Opcode::SCAS |
             Opcode::TEST |
+            Opcode::CMPSD |
+            Opcode::CMPSS |
             Opcode::CMP |
             Opcode::CMPXCHG => { write!(out, "{}", colors.comparison_op(self)) }
 
diff --git a/src/lib.rs b/src/lib.rs
index 6689bba..2884e7e 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -270,6 +270,7 @@ pub enum Opcode {
     MINSD,
     MAXSD,
     MOVSLDUP,
+    MOVSHDUP,
     MOVDDUP,
     HADDPS,
     HSUBPS,
@@ -277,11 +278,14 @@ pub enum Opcode {
     CVTSI2SS,
     CVTSI2SD,
     CVTTSD2SI,
+    CVTTPS2DQ,
+    CVTPD2DQ,
     CVTSD2SI,
     CVTSD2SS,
     CVTTSS2SI,
     CVTSS2SI,
     CVTSS2SD,
+    CVTDQ2PD,
     LDDQU,
     MOVSX_b,
     MOVSX_w,
@@ -292,6 +296,7 @@ pub enum Opcode {
     SAR,
     SAL,
     SHR,
+    SHRD,
     SHL,
     RCR,
     RCL,
@@ -433,6 +438,20 @@ pub enum Opcode {
     CLD,
     STD,
     JMPE,
+    POPCNT,
+    MOVDQU,
+    MOVQ,
+    CMPSS,
+    CMPSD,
+    UNPCKLPS,
+    UNPCKHPS,
+    PSHUFHW,
+    PSHUFLW,
+    MOVUPS,
+    MOVQ2DQ,
+    MOVDQ2Q,
+    RSQRTSS,
+    RCPSS,
 }
 #[derive(Debug)]
 pub struct Instruction {
@@ -671,8 +690,12 @@ pub enum OperandCode {
     AX_Ivd,
     ModRM_0x0f00,
     ModRM_0x0f01,
+    ModRM_0x0f12,
+    ModRM_0x0f13,
     ModRM_0x0fae,
     ModRM_0x0fba,
+    ModRM_0xf238,
+    ModRM_0xf30fc7,
     Rq_Cq_0,
     Rq_Dq_0,
     Cq_Rq_0,
@@ -719,6 +742,7 @@ pub enum OperandCode {
     Gv_Ew,
     Gv_Ed,
     G_E_xmm,
+    G_E_xmm_Ib,
     Gv_M,
     I_3,
     Ib,
@@ -768,7 +792,8 @@ pub enum OperandCode {
     Zv_Ivq_R6,
     Zv_Ivq_R7,
     Nothing,
-    Implied
+    Implied,
+    Unsupported,
 }
 
 fn base_opcode_map(v: u8) -> Opcode {
@@ -859,7 +884,7 @@ const OPCODE_F20F_MAP: [OpcodeRecord; 256] = [
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf238),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
@@ -919,7 +944,7 @@ const OPCODE_F20F_MAP: [OpcodeRecord; 256] = [
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
 // 0x70
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::PSHUFLW), OperandCode::G_E_xmm_Ib),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
@@ -1006,7 +1031,7 @@ const OPCODE_F20F_MAP: [OpcodeRecord; 256] = [
 // 0xc0
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CMPSD), OperandCode::G_E_xmm_Ib),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
@@ -1027,7 +1052,7 @@ const OPCODE_F20F_MAP: [OpcodeRecord; 256] = [
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVDQ2Q), OperandCode::Unsupported),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
@@ -1044,7 +1069,7 @@ const OPCODE_F20F_MAP: [OpcodeRecord; 256] = [
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CVTPD2DQ), OperandCode::G_E_xmm),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
@@ -1090,8 +1115,297 @@ fn read_opcode_f20f_map<T: Iterator<Item=u8>>(bytes_iter: &mut T, instruction: &
         }
     }
 }
+
+const OPCODE_F30F_MAP: [OpcodeRecord; 256] = [
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0x10
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVSS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVSS), OperandCode::E_G_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVSLDUP), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVSHDUP), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0x20
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CVTSI2SS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CVTTSS2SI), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CVTSS2SI), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0x30
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0x40
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0x50
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::SQRTSS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::RSQRTSS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::RCPSS), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::ADDSS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MULSS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CVTSS2SD), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CVTTPS2DQ), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::SUBSS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MINSS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::DIVSS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MAXSS), OperandCode::G_E_xmm),
+// 0x60
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVDQU), OperandCode::Nothing),
+// 0x70
+    OpcodeRecord(Interpretation::Instruction(Opcode::PSHUFHW), OperandCode::G_E_xmm_Ib),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVQ), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVDQU), OperandCode::E_G_xmm),
+// 0x80
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0x90
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0xa0
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0xb0
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::POPCNT), OperandCode::Gv_Ev),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0xc0
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CMPSS), OperandCode::G_E_xmm_Ib),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30fc7),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0xd0
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVQ2DQ), OperandCode::Unsupported),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0xe0
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::CVTDQ2PD), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+// 0xf0
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+];
+
 fn read_opcode_f30f_map<T: Iterator<Item=u8>>(bytes_iter: &mut T, instruction: &mut Instruction) -> Option<OpcodeRecord> {
-    return None;
+    match bytes_iter.next() {
+        Some(b) => {
+            instruction.length += 1;
+            let record = OPCODE_F30F_MAP[b as usize];
+            if let Interpretation::Instruction(opc) = record.0 {
+                instruction.opcode = opc;
+            } else {
+                unsafe { unreachable_unchecked(); }
+            }
+            Some(record)
+        }
+        None => {
+            None
+        }
+    }
     /*
     match bytes_iter.next() {
         Some(b) => {
@@ -1141,12 +1455,12 @@ const OPCODE_0F_MAP: [OpcodeRecord; 256] = [
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
 // 0x10
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVUPS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::MOVUPS), OperandCode::E_G_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f12),
+    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f13),
+    OpcodeRecord(Interpretation::Instruction(Opcode::UNPCKLPS), OperandCode::G_E_xmm),
+    OpcodeRecord(Interpretation::Instruction(Opcode::UNPCKHPS), OperandCode::G_E_xmm),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
@@ -1305,17 +1619,17 @@ const OPCODE_0F_MAP: [OpcodeRecord; 256] = [
     OpcodeRecord(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS),
     OpcodeRecord(Interpretation::Instruction(Opcode::POP), OperandCode::GS),
     OpcodeRecord(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::BT), OperandCode::Gv_Ev),
+    OpcodeRecord(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::PUSH), OperandCode::Nothing),
     OpcodeRecord(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS),
+    OpcodeRecord(Interpretation::Instruction(Opcode::POP), OperandCode::GS),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
-    OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+    OpcodeRecord(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv),
+    OpcodeRecord(Interpretation::Instruction(Opcode::SHRD), OperandCode::Unsupported),
+    OpcodeRecord(Interpretation::Instruction(Opcode::SHRD), OperandCode::Unsupported),
     OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae),
     OpcodeRecord(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev),
 
diff --git a/test/test.rs b/test/test.rs
index 5d5f3b0..722be16 100644
--- a/test/test.rs
+++ b/test/test.rs
@@ -70,6 +70,14 @@ fn test_E_decode() {
 #[test]
 fn test_sse() {
     test_display(&[0x0f, 0x28, 0xd0], "movaps xmm2, xmm0");
+    test_display(&[0x66, 0x0f, 0x28, 0xd0], "movapd xmm2, xmm0");
+    test_display(&[0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [rax]");
+    test_display(&[0x4f, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [rax]");
+    test_display(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8]");
+    test_display(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8]");
+    test_display(&[0x67, 0x4f, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [eax]");
+    test_display(&[0x67, 0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8d]");
+    test_display(&[0x66, 0x0f, 0x29, 0x00], "movapd xmmword [rax], xmm0");
     test_display(&[0x66, 0x0f, 0xef, 0xc0], "pxor xmm0, xmm0");
     test_display(&[0xf2, 0x0f, 0x10, 0x0c, 0xc6], "movsd xmm1, [rsi + rax * 8]");
     test_display(&[0xf3, 0x0f, 0x10, 0x04, 0x86], "movss xmm0, [rsi + rax * 4]");
@@ -150,6 +158,7 @@ fn test_push_pop() {
 fn test_bitwise() {
     test_display(&[0x41, 0x0f, 0xbc, 0xd3], "bsf edx, r11d");
     test_display(&[0x48, 0x0f, 0xa3, 0xd0], "bt rax, rdx");
+    test_display(&[0x48, 0x0f, 0xab, 0xd0], "bts rax, rdx");
 }
 
 #[test]
@@ -170,3 +179,123 @@ fn test_misc() {
     test_display(&[0xf3, 0x48, 0xa5], "rep movsq");
     test_display(&[0xf3, 0x45, 0x0f, 0xbc, 0xd7], "tzcnt r10d, r15d");
 }
+
+#[test]
+fn evex() {
+    test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x44, 0x40, 0x01], "vmovntdqa zmm0, zmmword [rax + rax*2 + 0x40]");
+    test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x44, 0x40, 0x01], "vmovntdqa xmm0, xmmword [rax + rax*2 + 0x10]");
+}
+
+#[test]
+fn vex() {
+}
+
+#[test]
+fn prefixed_0f() {
+    test_display(&[0x0f, 0x02, 0xc0], "lar eax, eax");
+    test_display(&[0x48, 0x0f, 0x02, 0xc0], "lar rax, eax");
+    test_display(&[0x0f, 0x03, 0xc0], "lsl eax, eax");
+    test_display(&[0x48, 0x0f, 0x03, 0xc0], "lsl rax, rax");
+    test_display(&[0x0f, 0x05], "syscall");
+    test_display(&[0x48, 0x0f, 0x05], "syscall");
+    test_display(&[0x66, 0x0f, 0x05], "syscall");
+    test_display(&[0x0f, 0x05], "sysret");
+    test_display(&[0xf2, 0x0f, 0x05], "sysret");
+    test_display(&[0x0f, 0x12, 0x0f], "movlps xmm1, qword [rdi]");
+    test_display(&[0x0f, 0x12, 0xc0], "movhlps xmm0, xmm0");
+    test_display(&[0x0f, 0x13, 0xc0], "invalid");
+    test_display(&[0x0f, 0x14, 0x00], "unpcklps xmm1, xmmword [rax]");
+    test_display(&[0x0f, 0x15, 0x00], "unpckhps xmm1, xmmword [rax]");
+    test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, qword [rdi]");
+    test_display(&[0x0f, 0x16, 0xc0], "movlhps xmm0, xmm0");
+    test_display(&[0x0f, 0x17, 0xc0], "invalid");
+    test_display(&[0x0f, 0x18, 0xc0], "invalid");
+    test_display(&[0x0f, 0x18, 0x00], "prefetchnta byte [rax]");
+    test_display(&[0x0f, 0x18, 0x08], "prefetch1 byte [rax]");
+    test_display(&[0x0f, 0x18, 0x10], "prefetch2 byte [rax]");
+    test_display(&[0x0f, 0x18, 0x18], "prefetch2 byte [rax]");
+    test_display(&[0x0f, 0x18, 0x20], "nop dword [rax]");
+    test_display(&[0x4f, 0x0f, 0x18, 0x20], "nop dword [rax]");
+    test_display(&[0x0f, 0x19, 0x20], "nop dword [rax]");
+    test_display(&[0x0f, 0x1a, 0x20], "nop dword [rax]");
+    test_display(&[0x0f, 0x1b, 0x20], "nop dword [rax]");
+    test_display(&[0x0f, 0x1c, 0x20], "nop dword [rax]");
+    test_display(&[0x0f, 0x1d, 0x20], "nop dword [rax]");
+    test_display(&[0x0f, 0x1e, 0x20], "nop dword [rax]");
+    test_display(&[0x0f, 0x1f, 0x20], "nop dword [rax]");
+    test_display(&[0x45, 0x0f, 0x20, 0xc8], "mov r8, cr9");
+    test_display(&[0x0f, 0x20, 0xc8], "mov rax, cr1");
+    test_display(&[0x45, 0x0f, 0x21, 0xc8], "mov r8, dr9");
+    test_display(&[0x0f, 0x21, 0xc8], "mov rax, dr1");
+    test_display(&[0x45, 0x0f, 0x22, 0xc8], "mov cr9, r8");
+    test_display(&[0x40, 0x0f, 0x22, 0xc8], "mov cr1, rax");
+    test_display(&[0x0f, 0x22, 0xc8], "mov cr1, rax");
+    test_display(&[0x44, 0x0f, 0x22, 0xcf], "mov cr9, rdi");
+    test_display(&[0x0f, 0x22, 0xcf], "mov cr1, rdi");
+    test_display(&[0x45, 0x0f, 0x23, 0xc8], "mov dr9, r8");
+    test_display(&[0x40, 0x0f, 0x23, 0xc8], "mov dr1, rax");
+    test_display(&[0x0f, 0x23, 0xc8], "mov dr1, rax");
+    test_display(&[0x44, 0x0f, 0x23, 0xcf], "mov dr9, rdi");
+    test_display(&[0x0f, 0x23, 0xcf], "mov dr1, rdi");
+    test_display(&[0x0f, 0x30], "wrmsr");
+    test_display(&[0x0f, 0x31], "rdtsc");
+    test_display(&[0x0f, 0x32], "rdmsr");
+    test_display(&[0x0f, 0x33], "rdpmc");
+    test_display(&[0x0f, 0x34], "sysenter");
+    test_display(&[0x0f, 0x35], "sysret");
+    test_display(&[0x0f, 0x36], "invalid");
+    test_display(&[0x0f, 0x37], "getsec");
+    test_display(&[0x0f, 0x60, 0x00], "punpcklbw mm0, qword [rax]");
+    test_display(&[0x0f, 0x61, 0x00], "punpcklwd mm0, qword [rax]");
+    test_display(&[0x0f, 0x62, 0x00], "punpckldq mm0, qword [rax]");
+    test_display(&[0x0f, 0x63, 0x00], "packsswb mm0, qword [rax]");
+    test_display(&[0x0f, 0x64, 0x00], "pcmpgtb mm0, qword [rax]");
+    test_display(&[0x0f, 0x65, 0x00], "pcmpgtw mm0, qword [rax]");
+    test_display(&[0x0f, 0x66, 0x00], "pcmpgtd mm0, qword [rax]");
+    test_display(&[0x0f, 0x67, 0x00], "packuswb mm0, qword [rax]");
+    test_display(&[0x0f, 0x68, 0x00], "punpckhbw mm0, qword [rax]");
+    test_display(&[0x0f, 0x69, 0x00], "punpckhbd mm0, qword [rax]");
+    test_display(&[0x0f, 0x6a, 0x00], "punpckhdq mm0, qword [rax]");
+    test_display(&[0x0f, 0x6b, 0x00], "packssdw mm0, qword [rax]");
+    test_display(&[0x0f, 0x6c], "invalid");
+    test_display(&[0x0f, 0x6d], "invalid");
+    test_display(&[0x0f, 0x6e], "movd mm0, dword [rax]");
+    test_display(&[0x0f, 0x6f], "movd mm0, qword [rax]");
+    test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [rax], 0x7f");
+    test_display(&[0x0f, 0x71, 0xd0, 0x7f], "psrlw mm0, 0x7f");
+    test_display(&[0x0f, 0x71, 0xe0, 0x7f], "psraw mm0, 0x7f");
+    test_display(&[0x0f, 0x71, 0xf0, 0x7f], "psllw mm0, 0x7f");
+    test_display(&[0x0f, 0x72, 0xd0, 0x7f], "psrld mm0, 0x7f");
+    test_display(&[0x0f, 0x72, 0xe0, 0x7f], "psrad mm0, 0x7f");
+    test_display(&[0x0f, 0x72, 0xf0, 0x7f], "pslld mm0, 0x7f");
+    test_display(&[0x0f, 0xa0], "push fs");
+    test_display(&[0x0f, 0xa1], "pop fs");
+    test_display(&[0x0f, 0xa2], "cpuid");
+    test_display(&[0x0f, 0xa4, 0xc0, 0x11], "shld eax, eax, 0x11");
+    test_display(&[0x0f, 0xa5, 0xc0], "shld eax, eax, cl");
+    test_display(&[0x0f, 0xa5, 0xc9], "shld ecx, ecx, cl");
+}
+
+#[test]
+fn prefixed_660f() {
+    test_display(&[0x66, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm0");
+    test_display(&[0x66, 0x48, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm0");
+    test_display(&[0x66, 0x49, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm8");
+    test_display(&[0x66, 0x4a, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm8");
+    test_display(&[0x66, 0x4c, 0x0f, 0x10, 0xc0], "movupd xmm8, xmm0");
+    test_display(&[0x66, 0x4d, 0x0f, 0x10, 0xc0], "movupd xmm8, xmm8");
+    test_display(&[0xf2, 0x66, 0x66, 0x4d, 0x0f, 0x10, 0xc0], "movupd xmm8, xmm8");
+}
+
+#[test]
+fn prefixed_f20f() {
+    test_display(&[0xf2, 0x0f, 0x16, 0xcf], "movlhps xmm1, xmm7");
+    test_display(&[0xf2, 0x4d, 0x0f, 0x16, 0xcf], "movlhps xmm9, xmm15");
+    test_display(&[0x40, 0x66, 0xf2, 0x66, 0x4d, 0x0f, 0x16, 0xcf], "movlhps xmm9, xmm15");
+}
+
+#[test]
+fn prefixed_f30f() {
+    test_display(&[0xf3, 0x0f, 0x16, 0xcf], "movshdup xmm1, xmm7");
+    test_display(&[0xf3, 0x4d, 0x0f, 0x16, 0xcf], "movshdup xmm9, xmm15");
+}