add tsxldtrk

does intel know no bounds

3 files changed, 31 insertions, 0 deletions

diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs
index 997a9a9..8750cc6 100644
--- a/src/long_mode/display.rs
+++ b/src/long_mode/display.rs
@@ -1311,6 +1311,10 @@ const MNEMONICS: &[&'static str] = &[
     "clui",
     "stui",
     "senduipi",
+
+    // TSXLDTRK
+    "xsusldtrk",
+    "xresldtrk",
 ];
 
 impl Opcode {
@@ -2321,6 +2325,8 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> Colorize<T, Color
             Opcode::CLUI |
             Opcode::STUI |
             Opcode::SENDUIPI |
+            Opcode::XSUSLDTRK |
+            Opcode::XRESLDTRK |
             Opcode::LAR => { write!(out, "{}", colors.platform_op(self)) }
 
             Opcode::CRC32 |
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 6a85542..2c4ac92 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -1966,6 +1966,10 @@ pub enum Opcode {
     CLUI,
     STUI,
     SENDUIPI,
+
+    // TSXLDTRK
+    XSUSLDTRK,
+    XRESLDTRK,
 }
 
 #[derive(Debug)]
@@ -8326,6 +8330,12 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
                 let m = modrm & 7;
                 match m {
                     0b000 => {
+                        if instruction.prefixes.repnz() {
+                            instruction.opcode = Opcode::XSUSLDTRK;
+                            instruction.operands[0] = OperandSpec::Nothing;
+                            instruction.operand_count = 0;
+                            return Ok(());
+                        }
                         if !instruction.prefixes.rep() || instruction.prefixes.repnz() {
                             return Err(DecodeError::InvalidOpcode);
                         }
@@ -8333,6 +8343,15 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
                         instruction.operands[0] = OperandSpec::Nothing;
                         instruction.operand_count = 0;
                     }
+                    0b001 => {
+                        if instruction.prefixes.repnz() {
+                            instruction.opcode = Opcode::XRESLDTRK;
+                            instruction.operands[0] = OperandSpec::Nothing;
+                            instruction.operand_count = 0;
+                            return Ok(());
+                        }
+                        return Err(DecodeError::InvalidOpcode);
+                    }
                     0b010 => {
                         if !instruction.prefixes.rep() || instruction.prefixes.repnz() {
                             return Err(DecodeError::InvalidOpcode);
diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs
index 8110d44..1895f6e 100644
--- a/test/long_mode/mod.rs
+++ b/test/long_mode/mod.rs
@@ -2377,3 +2377,9 @@ fn test_tdx() {
     test_display(&[0x66, 0x0f, 0x01, 0xce], "seamops");
     test_display(&[0x66, 0x0f, 0x01, 0xcf], "seamcall");
 }
+
+#[test]
+fn test_tsxldtrk() {
+    test_display(&[0xf2, 0x0f, 0x01, 0xe8], "xsusldtrk");
+    test_display(&[0xf2, 0x0f, 0x01, 0xe9], "xresldtrk");
+}