diff options
| author | iximeow <me@iximeow.net> | 2020-07-26 04:20:35 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2020-07-26 04:20:35 -0700 |
| commit | f6c153d4cf511d05d8f1df21190b73d62c2412bb (patch) | |
| tree | b2584dd3a9c1d3aa9895a0a04b8d0e4787929554 | |
| parent | c54b230323e49222d188b409a1efa9dc99c62ec6 (diff) | |
bitwise ops, test cases, btr
| -rw-r--r-- | src/long_mode/mod.rs | 4 | ||||
| -rw-r--r-- | test/long_mode/mod.rs | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 1b80b11..fe490e8 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -5492,12 +5492,16 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, op @ OperandCode::ModRM_0xc1_Ev_Ib | op @ OperandCode::ModRM_0xd0_Eb_1 | op @ OperandCode::ModRM_0xd1_Ev_1 | + op @ OperandCode::ModRM_0xd2_Eb_CL | op @ OperandCode::ModRM_0xd3_Ev_CL => { instruction.operands[0] = mem_oper; instruction.opcode = BITWISE_OPCODE_MAP[((modrm >> 3) & 7) as usize].clone(); if let OperandCode::ModRM_0xd3_Ev_CL = op { instruction.modrm_rrr = RegSpec::cl(); instruction.operands[1] = OperandSpec::RegRRR; + } else if let OperandCode::ModRM_0xd2_Eb_CL = op { + instruction.modrm_rrr = RegSpec::cl(); + instruction.operands[1] = OperandSpec::RegRRR; } else { let num = match op { OperandCode::ModRM_0xc0_Eb_Ib | diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs index 545a2d5..2ddb7d1 100644 --- a/test/long_mode/mod.rs +++ b/test/long_mode/mod.rs @@ -967,6 +967,10 @@ fn test_bitwise() { test_display_under(&InstDecoder::minimal(), &[0x41, 0x0f, 0xbc, 0xd3], "bsf edx, r11d"); test_display(&[0x48, 0x0f, 0xa3, 0xd0], "bt rax, rdx"); test_display(&[0x48, 0x0f, 0xab, 0xd0], "bts rax, rdx"); + test_display(&[0x48, 0x0f, 0xb3, 0xd0], "btr rax, rdx"); + test_display(&[0x0f, 0xb3, 0xd0], "btr eax, edx"); + test_display(&[0x66, 0x41, 0x0f, 0xb3, 0xc0], "btr r8w, ax"); + test_display(&[0xd2, 0xe0], "shl al, cl"); } #[test] |