diff options
| author | iximeow <me@iximeow.net> | 2026-06-06 04:14:51 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-06-21 16:44:21 +0000 |
| commit | 9c676ba70cdbf0edfeae7b8a13e881724711383b (patch) | |
| tree | c7a39d37c00069b3323559840aa4f52f0c2393ac | |
| parent | d8d1662bc0469901a25658679e07082aa4d71d22 (diff) | |
the weird 64b movq thing was a capstone bug all along?!
| -rw-r--r-- | src/long_mode/mod.rs | 21 | ||||
| -rw-r--r-- | src/protected_mode/mod.rs | 1 | ||||
| -rw-r--r-- | src/real_mode/mod.rs | 1 | ||||
| -rw-r--r-- | test/long_mode/mod.rs | 4 |
4 files changed, 8 insertions, 19 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 9f04198..01b2f08 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -7242,24 +7242,11 @@ fn read_operands< instruction.operand_count = 2; instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; - if instruction.prefixes.rex_unchecked().w() { - let op = instruction.operands[0]; - instruction.operands[0] = instruction.operands[1]; - instruction.operands[1] = op; - instruction.regs[0].bank = RegisterBank::MM; - instruction.regs[0].num &= 0b111; - instruction.opcode = Opcode::MOVD; - if instruction.operands[1] != OperandSpec::RegMMM { - instruction.mem_size = 4; - } else { - instruction.regs[1].bank = RegisterBank::Q; - } + + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 8; } else { - if instruction.operands[1] != OperandSpec::RegMMM { - instruction.mem_size = 8; - } else { - instruction.regs[1].bank = RegisterBank::X; - } + instruction.regs[1].bank = RegisterBank::X; } } OperandCase::ModRM_0x0f0d => { diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs index 0c33643..5476647 100644 --- a/src/protected_mode/mod.rs +++ b/src/protected_mode/mod.rs @@ -7157,6 +7157,7 @@ fn read_operands< instruction.operand_count = 2; instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; + if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { diff --git a/src/real_mode/mod.rs b/src/real_mode/mod.rs index 334c07a..ee66d2a 100644 --- a/src/real_mode/mod.rs +++ b/src/real_mode/mod.rs @@ -7199,6 +7199,7 @@ fn read_operands< instruction.operand_count = 2; instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; + if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs index 9c3039d..80c90bb 100644 --- a/test/long_mode/mod.rs +++ b/test/long_mode/mod.rs @@ -1559,12 +1559,12 @@ mod sse { ), testcase!(&[0xf3, 0x0f, 0x70, 0xc0, 0x4e], "pshufhw xmm0, xmm0, 0x4e"), testcase!(&[0xf3, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"), - testcase!(&[0xf3, 0x4f, 0x0f, 0x7e, 0xc1], "movd r9, mm0"), + testcase!(&[0xf3, 0x4f, 0x0f, 0x7e, 0xc1], "movq xmm8, xmm9"), testcase!(&[0xf3, 0x40, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"), testcase!(&[0xf3, 0x41, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm9"), testcase!(&[0xf3, 0x42, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"), testcase!(&[0xf3, 0x44, 0x0f, 0x7e, 0xc1], "movq xmm8, xmm1"), - testcase!(&[0xf3, 0x48, 0x0f, 0x7e, 0xc1], "movd rcx, mm0"), + testcase!(&[0xf3, 0x48, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"), testcase!( &[0xf3, 0x4f, 0x0f, 0x7f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movdqu xmmword [r12 + r11 * 4 - 0x334455cc], xmm11" |