working through a bunch of avx512 stuff..

5 files changed, 252 insertions, 34 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 54f1ada..40e8e5a 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -32,6 +32,8 @@
   always decoded as ymm.
 * vmaskmovqdu now reports a memory access size for the implied write to ds:[rdi/edi/di].
 * correct swapped operand order of 0xD6-opcode movq.
+* reject so many invalid AVX512 encodings (instructions which do not support broadcast,
+  or rounding, or require W=0/W=1, etc).
 * some instructions (such as invept, invvpid) were accepted by uarch-specific
   deocders when they should not have been.
 
diff --git a/src/isa_settings.rs b/src/isa_settings.rs
index 76eb795..20d2e3f 100644
--- a/src/isa_settings.rs
+++ b/src/isa_settings.rs
@@ -77,12 +77,50 @@ macro_rules! gen_isa_settings {
             )*
         }
 
+        // only present in Knights Mill
+        static AVX512_4FMAPS: &[Opcode] = &[
+            Opcode::V4FMADDPS,
+            Opcode::V4FNMADDPS,
+            Opcode::V4FMADDSS,
+            Opcode::V4FNMADDSS,
+        ];
+
+        // only present in Knights Mill
+        static AVX512_4VNNIW: &[Opcode] = &[
+            Opcode::VP4DPWSSDS,
+            Opcode::VP4DPWSSD,
+        ];
+
         /// optionally reject or reinterpret instruction according to settings for this decode
         /// operation.
         pub(crate) fn revise_instruction(settings: &$featureful_decoder, inst: &mut $inst_ty) -> Result<(), $decode_err> {
             if inst.prefixes.evex().is_some() {
+                // TODO: this happens to be the set of features on a Zen 5 processor..
+                let avx512_baseline = settings.avx512_f()
+                    && settings.avx512_dq()
+                    && settings.avx512_fma()
+                    && settings.avx512_cd()
+                    && settings.avx512_bw()
+                    && settings.avx512_vl()
+                    && settings.avx512_vbmi()
+                    && settings.avx512_vbmi2()
+                    && settings.avx512_vnni()
+                    && settings.avx512_bitalg()
+                    && settings.avx512_vpopcntdq();
+
                 if !settings.avx512() {
-                    return Err(<$decode_err>::InvalidOpcode);
+                    if !settings.avx512_4vnniw() && AVX512_4VNNIW.contains(&inst.opcode) {
+                        return Err(<$decode_err>::InvalidOpcode);
+                    } else if !settings.avx512_4fmaps() && AVX512_4FMAPS.contains(&inst.opcode) {
+                        return Err(<$decode_err>::InvalidOpcode);
+                    } else if avx512_baseline {
+                        // TODO: hack around missing avx feature set specificity.
+                        return Ok(());
+                    } else {
+                        // TODO: if settings.with_avx512(false) == *settings {
+                        // truly no AVX512 at all..
+                        return Err(<$decode_err>::InvalidOpcode);
+                    }
                 } else {
                     return Ok(());
                 }
@@ -830,6 +868,8 @@ macro_rules! gen_arch_isa_settings {
             avx512_vbmi2, with_avx512_vbmi2 = 21;
             avx512_vl, with_avx512_vl = 22;
             avx512_vpopcntdq, with_avx512_vpopcntdq = 23;
+            // TODO: VP2INTERSECTD
+            // avx512_vp2intersectd, with_avx512_vp2intersectq = ;
             avx_vnni, with_avx_vnni = 24;
             bmi1, with_bmi1 = 25;
             #[doc="`bmi2` indicates support for the `BZHI`, `MULX`, `PDEP`, `PEXT`, `RORX`, `SARX`, `SHRX`, "]
diff --git a/src/shared/evex.in b/src/shared/evex.in
index 0aa7d95..a15b59b 100644
--- a/src/shared/evex.in
+++ b/src/shared/evex.in
@@ -1,6 +1,7 @@
 use super::OperandSpec;
 use super::FieldDescription;
 use super::InnerDescription;
+use super::Prefixes;
 
 use yaxpeax_arch::annotation::DescriptionSink;
 
@@ -312,6 +313,23 @@ fn check_mask_reg(inst: &Instruction) -> Result<(), DecodeError> {
 }
 
 #[inline(always)]
+fn check_allowed_zero_merge(prefixes: &Prefixes, oper: OperandSpec) -> Result<(), DecodeError> {
+  if prefixes.evex_unchecked().merge() {
+    // if evex.z is set
+
+    if oper.is_memory() {
+      // quoth APM,
+      // > 3.2.4 Exceptions Caused by Illegal EVEX encodings
+      // > ..
+      // > EVEX.z == 1 ... Instructions that do not specify {z} ... #UD
+      return Err(DecodeError::InvalidOperand);
+    }
+  }
+
+  Ok(())
+}
+
+#[inline(always)]
 fn apply_broadcast(inst: &mut Instruction, item_size: u8, reg_size: u8) {
   if inst.prefixes.evex_unchecked().broadcast() {
     inst.mem_size = item_size;
@@ -436,6 +454,8 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().vex().w() {
         if instruction.opcode == Opcode::VRSQRT14SS {
           instruction.opcode = Opcode::VRSQRT14SD;
+        } else if instruction.opcode == Opcode::VRCP14SS {
+          instruction.opcode = Opcode::VRCP14SD;
         }
       }
 
@@ -471,6 +491,10 @@ pub(crate) fn read_evex_operands<
       } else {
         if instruction.prefixes.evex_unchecked().broadcast() {
           return Err(DecodeError::InvalidOpcode);
+        } else {
+          if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+            return Err(DecodeError::InvalidOpcode);
+          }
         }
         instruction.mem_size = 8;
       }
@@ -488,12 +512,6 @@ pub(crate) fn read_evex_operands<
 
       instruction.operand_count = 3;
 
-      if instruction.prefixes.evex_unchecked().vex().w() {
-        if instruction.opcode == Opcode::VGETEXPSS {
-          instruction.opcode = Opcode::VGETEXPSD;
-        }
-      }
-
       if let OperandSpec::RegMMM = mem_oper {
         if instruction.prefixes.evex_unchecked().broadcast() {
           instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
@@ -900,6 +918,9 @@ pub(crate) fn read_evex_operands<
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operand_count = 3;
 
       set_reg_sizes_from_ll(instruction)?;
@@ -945,12 +966,14 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.operands[0] = mem_oper.masked();
       instruction.operands[1] = OperandSpec::RegRRR;
       instruction.operand_count = 2;
@@ -981,7 +1004,7 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Gm_Eq_xmm_sae_W1 => {
       deny_vex_reg(instruction)?;
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
       // vucomisd and vcomisd both are W=1
       ensure_W(instruction, 1)?;
 
@@ -1005,6 +1028,7 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
@@ -1126,7 +1150,7 @@ pub(crate) fn read_evex_operands<
         }
       } else {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
-        apply_broadcast(instruction, 8, sz);
+        apply_broadcast(instruction, 4, sz);
         set_reg_sizes_from_ll(instruction)?;
       }
     }
@@ -1444,6 +1468,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      if instruction.prefixes.evex_unchecked().broadcast() && !mem_oper.is_memory() {
+        return Err(DecodeError::InvalidOpcode);
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
@@ -1571,6 +1598,9 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if instruction.prefixes.evex_unchecked().broadcast() {
+        if mem_oper.is_memory() {
+           return Err(DecodeError::InvalidOperand);
+        }
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
         if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
@@ -1595,8 +1625,6 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().vex().w() {
         if instruction.opcode == Opcode::VSCALEFSS {
           instruction.opcode = Opcode::VSCALEFSD;
-        } else if instruction.opcode == Opcode::VRCP14SS {
-          instruction.opcode = Opcode::VRCP14SD;
         }
       }
 
@@ -1604,6 +1632,9 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if instruction.prefixes.evex_unchecked().broadcast() {
+        if mem_oper.is_memory() {
+          return Err(DecodeError::InvalidOpcode);
+        };
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
       } else {
         if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
@@ -1626,6 +1657,44 @@ pub(crate) fn read_evex_operands<
       }
       set_reg_sizes(instruction, RegisterBank::X);
     }
+    generated::EVEXOperandCode::Gm_V_Ed_xmm_sae_noround => {
+      check_mask_reg(instruction)?;
+
+      if instruction.prefixes.evex_unchecked().vex().w() {
+        if instruction.opcode == Opcode::VGETEXPSS {
+          instruction.opcode = Opcode::VGETEXPSD;
+        }
+      }
+
+      let modrm = read_modrm(words)?;
+      set_rrr(instruction, modrm);
+      let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if instruction.prefixes.evex_unchecked().broadcast() {
+        if mem_oper.is_memory() {
+          return Err(DecodeError::InvalidOpcode);
+        };
+        instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
+      } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOperand);
+        }
+        instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
+      }
+      instruction.operands[1] = OperandSpec::RegVex;
+      instruction.operands[2] = mem_oper;
+      instruction.operand_count = 3;
+
+      if mem_oper == OperandSpec::RegMMM {
+        instruction.mem_size = 0;
+      } else {
+        if instruction.prefixes.evex_unchecked().vex().w() {
+          instruction.mem_size = 8;
+        } else {
+          instruction.mem_size = 4;
+        }
+      }
+      set_reg_sizes(instruction, RegisterBank::X);
+    }
     generated::EVEXOperandCode::Gm_V_Ed_xmm_sae_W0 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
@@ -1966,6 +2035,7 @@ pub(crate) fn read_evex_operands<
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2001,8 +2071,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Gm_ymm_E_xmm_W0 => {
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
-      ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2039,6 +2109,7 @@ pub(crate) fn read_evex_operands<
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2080,6 +2151,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Z;
       instruction.mem_size = 32;
       instruction.operands[0] = mem_oper.masked();
@@ -2095,6 +2167,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Z;
       instruction.mem_size = 16;
       instruction.operands[0] = mem_oper.masked();
@@ -2110,6 +2183,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Y;
       instruction.mem_size = 16;
       instruction.operands[0] = mem_oper.masked();
@@ -2125,6 +2199,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Z;
       instruction.mem_size = 8;
       instruction.operands[0] = mem_oper.masked();
@@ -2140,6 +2215,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::X;
       instruction.mem_size = 8;
       instruction.operands[0] = mem_oper.masked();
@@ -2155,6 +2231,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Y;
       instruction.mem_size = 4;
       instruction.operands[0] = mem_oper.masked();
@@ -2170,6 +2247,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::X;
       instruction.mem_size = 4;
       instruction.operands[0] = mem_oper.masked();
@@ -2185,6 +2263,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::X;
       instruction.mem_size = 2;
       instruction.operands[0] = mem_oper.masked();
@@ -2200,6 +2279,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.regs[0].bank = RegisterBank::Y;
       instruction.mem_size = 8;
       instruction.operands[0] = mem_oper.masked();
@@ -2659,6 +2739,11 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Mask_V_E_LL_bcast => {
       check_mask_reg(instruction)?;
+      deny_z(instruction)?;
+
+      if instruction.opcode == Opcode::VP2INTERSECTD {
+        deny_mask_reg(instruction)?;
+      }
 
       let sz = regs_size(instruction);
 
@@ -2680,6 +2765,7 @@ pub(crate) fn read_evex_operands<
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if mem_oper == OperandSpec::RegMMM {
         instruction.mem_size = 0;
+        deny_broadcast(instruction)?;
       }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
@@ -2696,6 +2782,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL_bcast_W1 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2704,7 +2791,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
         instruction.mem_size = 0;
       }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
@@ -2722,6 +2811,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL_bcast_W0 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2731,6 +2821,7 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
         instruction.mem_size = 0;
       }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
@@ -2773,6 +2864,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         instruction.mem_size = 0;
       }
@@ -2959,6 +3051,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         instruction.mem_size = 0;
       }
@@ -2990,6 +3083,7 @@ pub(crate) fn read_evex_operands<
       };
       instruction.regs[0].bank = r_sz;
       if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
         instruction.mem_size = 0;
         instruction.regs[1].bank = m_sz;
       } else {
@@ -3007,6 +3101,8 @@ pub(crate) fn read_evex_operands<
           instruction.opcode = Opcode::VPLZCNTQ;
         } else if instruction.opcode == Opcode::VRCP14PS {
           instruction.opcode = Opcode::VRCP14PD;
+        } else if instruction.opcode == Opcode::VRSQRT14PS {
+          instruction.opcode = Opcode::VRSQRT14PD;
         } else if instruction.opcode == Opcode::VPOPCNTD {
           instruction.opcode = Opcode::VPOPCNTQ;
         } else if instruction.opcode == Opcode::VPCONFLICTD {
@@ -3086,6 +3182,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Gm_LL_Ud => {
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
+      deny_broadcast(instruction)?;
 
       if instruction.prefixes.evex_unchecked().vex().w() && isa_has_qwords() {
         if instruction.opcode == Opcode::VPBROADCASTD {
@@ -3120,6 +3217,7 @@ pub(crate) fn read_evex_operands<
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_broadcast(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3355,8 +3453,6 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().vex().w() {
         if instruction.opcode == Opcode::VGETEXPPS {
           instruction.opcode = Opcode::VGETEXPPD;
-        } else if instruction.opcode == Opcode::VRSQRT14PS {
-          instruction.opcode = Opcode::VRSQRT14PD;
         }
       }
 
@@ -3380,11 +3476,7 @@ pub(crate) fn read_evex_operands<
             4
           }, sz);
         } else {
-          if instruction.opcode == Opcode::VSQRTPS || instruction.opcode == Opcode::VCVTPS2DQ {
-            instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
-          } else {
-            instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
-          }
+          instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
           set_reg_sizes(instruction, RegisterBank::Z);
         }
       } else {
@@ -3520,6 +3612,7 @@ pub(crate) fn read_evex_operands<
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3546,6 +3639,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL => {
       check_mask_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -4235,6 +4329,7 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::VCVTPH2PS => {
       check_mask_reg(instruction)?;
+      ensure_W(instruction, 0)?;
       deny_vex_reg(instruction)?;
 
       if instruction.opcode == Opcode::VCVTPS2PD {
@@ -4248,6 +4343,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if instruction.opcode == Opcode::VCVTPH2PS && mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = mem_oper;
       instruction.operand_count = 2;
@@ -4527,6 +4625,15 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if !instruction.prefixes.evex_unchecked().broadcast() {
+        if instruction.prefixes.evex_unchecked().lp() {
+          if instruction.prefixes.evex_unchecked().vex().l() {
+            return Err(DecodeError::InvalidOperand);
+          }
+        }
+      } else if mem_oper.is_memory() {
+        return Err(DecodeError::InvalidOperand);
+      }
 
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
@@ -4918,6 +5025,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VMOVSD_10 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4940,10 +5048,12 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VMOVSD_11 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.operands[0] = mem_oper.masked();
       if mem_oper == OperandSpec::RegMMM {
         instruction.operands[1] = OperandSpec::RegVex;
@@ -4962,12 +5072,16 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VMOVSS_10 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       if mem_oper == OperandSpec::RegMMM {
+        if instruction.prefixes.evex_unchecked().broadcast() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[1] = OperandSpec::RegVex;
         instruction.operands[2] = mem_oper;
         instruction.operand_count = 3;
@@ -4984,10 +5098,12 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VMOVSS_11 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.operands[0] = mem_oper.masked();
       if mem_oper == OperandSpec::RegMMM {
         instruction.operands[1] = OperandSpec::RegVex;
@@ -5004,7 +5120,7 @@ pub(crate) fn read_evex_operands<
       set_reg_sizes(instruction, RegisterBank::X);
     }
     generated::EVEXOperandCode::VCVTSI2SS => {
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
       deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
@@ -5049,7 +5165,7 @@ pub(crate) fn read_evex_operands<
       }
     }
     generated::EVEXOperandCode::VCVTTSS2SI => {
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
       deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
@@ -5076,7 +5192,7 @@ pub(crate) fn read_evex_operands<
       instruction.operand_count = 2;
     }
     generated::EVEXOperandCode::VCVTSS2SI => {
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
       deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
diff --git a/src/shared/generated_evex.in b/src/shared/generated_evex.in
index b2ca667..f2ccc76 100644
--- a/src/shared/generated_evex.in
+++ b/src/shared/generated_evex.in
@@ -593,6 +593,7 @@ pub(crate) enum EVEXOperandCode {
   Gm_V_Ed_xmm_sae,
   Gm_V_Ed_xmm_sae_W0,
   Gm_V_Ed_xmm_sae_bcast,
+  Gm_V_Ed_xmm_sae_noround,
   Gm_V_Ed_xmm_sae_noround_W0,
   Gm_V_Eq_xmm_sae_W1,
   Gm_V_LL_E_xmm,
@@ -701,12 +702,12 @@ const EVEX_None_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 30] = [
   (0x15, [(super::Opcode::VUNPCKHPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VUNPCKHPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VUNPCKHPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x16, [(super::Opcode::Invalid, EVEXOperandCode::Operands_16_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x17, [(super::Opcode::VMOVHPS, EVEXOperandCode::Mq_G_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x28, [(super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0x28, [(super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x29, [(super::Opcode::VMOVAPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2b, [(super::Opcode::VMOVNTPS, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTPS, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTPS, EVEXOperandCode::M_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2e, [(super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0)]),
   (0x2f, [(super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0)]),
-  (0x51, [(super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast)]),
+  (0x51, [(super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0)]),
   (0x54, [(super::Opcode::VANDPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x55, [(super::Opcode::VANDNPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDNPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDNPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x56, [(super::Opcode::VORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -749,7 +750,7 @@ const EVEX_66_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 100] = [
   (0x58, [(super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
   (0x59, [(super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
   (0x5a, [(super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_xmm_E_xmm_sae_bcast_W1), (super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_xmm_E_ymm_sae_bcast_W1), (super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_ymm_E_zmm_sae_bcast_W1), (super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_ymm_U_zmm_sae_W1)]),
-  (0x5b, [(super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast)]),
+  (0x5b, [(super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast_W0)]),
   (0x5c, [(super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
   (0x5d, [(super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
   (0x5e, [(super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]),
@@ -883,15 +884,15 @@ const EVEX_66_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 143] = [
   (0x3f, [(super::Opcode::VPMAXUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMAXUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMAXUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x40, [(super::Opcode::VPMULLD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMULLD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMULLD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x42, [(super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast)]),
-  (0x43, [(super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast)]),
+  (0x43, [(super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround)]),
   (0x44, [(super::Opcode::VPLZCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPLZCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPLZCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x45, [(super::Opcode::VPSRLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x46, [(super::Opcode::VPSRAVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRAVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRAVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x47, [(super::Opcode::VPSLLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSLLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSLLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x4c, [(super::Opcode::VRCP14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRCP14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRCP14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x4d, [(super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae)]),
-  (0x4e, [(super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x4f, [(super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm)]),
+  (0x4d, [(super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0x4e, [(super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0x4f, [(super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x50, [(super::Opcode::VPDPBUSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x51, [(super::Opcode::VPDPBUSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x52, [(super::Opcode::VPDPWSSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPWSSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPWSSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -1031,8 +1032,8 @@ const EVEX_66_0f3a: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 51] = [
 ];
 
 const EVEX_f2_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 26] = [
-  (0x10, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10)]),// W0
-  (0x11, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11)]),// W0
+  (0x10, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W0
+  (0x11, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W0
   (0x12, [(super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x16, [(super::Opcode::VMOVSHDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSHDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSHDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2a, [(super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS)]),
@@ -1091,8 +1092,8 @@ const EVEX_f2_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 28] = [
 ];
 
 const EVEX_f3_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 24] = [
-  (0x10, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10)]),// W1
-  (0x11, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11)]),// W1
+  (0x10, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W1
+  (0x11, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W1
   (0x12, [(super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2a, [(super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS)]),
   (0x2c, [(super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae)]),
@@ -1104,7 +1105,7 @@ const EVEX_f3_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 24] = [
   (0x5c, [(super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]),
   (0x5d, [(super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]),// W1
   (0x5e, [(super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]),
-  (0x5f, [(super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae)]),// W1
+  (0x5f, [(super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]),// W1
   (0x6f, [(super::Opcode::VMOVDQU8, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x70, [(super::Opcode::VPSHUFLW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::VPSHUFLW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::VPSHUFLW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x78, [(super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae)]),
diff --git a/test/long_mode/evex_generated.rs b/test/long_mode/evex_generated.rs
index 46d99a7..48ab803 100644
--- a/test/long_mode/evex_generated.rs
+++ b/test/long_mode/evex_generated.rs
@@ -118,6 +118,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0xca], "vmovups xmm2{k5}, xmm1"); // VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0x0a], "vmovups xmmword [rdx], xmm1"); // VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x0a], "vmovups xmmword [rdx]{k5}, xmm1"); // VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0xca], "vmovhlps xmm1, xmm0, xmm2"); // VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x0a], "vmovlps xmm1, xmm0, qword [rdx]"); // VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x13, 0x0a], "vmovlps qword [rdx], xmm1"); // VMOVLPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX
@@ -180,6 +181,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x0a], "vmovhps qword [rdx], xmm1"); // VMOVHPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0xca], "vmovaps ymm1{k5}{z}, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0x0a], "vmovaps ymm1{k5}{z}, ymmword [rdx]"); // VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xbd, 0x28, 0x0a]); // no broadcast
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0xca], "vmovaps ymm1, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0xca], "vmovaps ymm1{k5}, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0x0a], "vmovaps ymm1, ymmword [rdx]"); // VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
@@ -207,6 +209,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0x0a], "vmovaps zmmword [rdx], zmm1"); // VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0x0a], "vmovaps zmmword [rdx]{k5}, zmm1"); // VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x29, 0xca], "vmovaps xmm2{k5}{z}, xmm1"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x9d, 0x29, 0xca]); // no sae/er support on movaps
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0xca], "vmovaps xmm2, xmm1"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0xca], "vmovaps xmm2{k5}, xmm1"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0x0a], "vmovaps xmmword [rdx], xmm1"); // VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
@@ -221,6 +224,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0xca], "vcomiss xmm1, xmm2"); // VCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x0a], "vcomiss xmm1, dword [rdx]"); // VCOMISS_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rz-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfc, 0xfd, 0x51, 0xca]); // requires W=0
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x51, 0xca], "vsqrtps zmm1{rz-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x51, 0xca], "vsqrtps zmm1{k5}{rz-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rd-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX
@@ -447,6 +451,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0x0a], "vmulps xmm1{k5}, xmm0, xmmword [rdx]"); // VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{z}{sae}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5a, 0xca], "vcvtps2pd zmm1{sae}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x78, 0x5a, 0xca]); // W=0
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{sae}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}{z}, dword [rdx]{1to4}"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5a, 0x0a], "vcvtps2pd ymm1, dword [rdx]{1to4}"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
@@ -888,6 +893,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0x0a], "vmovupd ymm1{k5}, ymmword [rdx]"); // VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0xca], "vmovupd zmm1{k5}{z}, zmm2"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0x0a], "vmovupd zmm1{k5}{z}, zmmword [rdx]"); // VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xdd, 0x10, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0xca], "vmovupd zmm1, zmm2"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0xca], "vmovupd zmm1{k5}, zmm2"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0x0a], "vmovupd zmm1, zmmword [rdx]"); // VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -919,6 +925,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x14, 0x0a], "vunpcklpd ymm1, ymm0, qword [rdx]{1to4}"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x14, 0x0a], "vunpcklpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0xca], "vunpcklpd ymm1{k5}{z}, ymm0, ymm2"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0xca]); // no broadcast in reg-reg
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0x0a], "vunpcklpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0xca], "vunpcklpd ymm1, ymm0, ymm2"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0xca], "vunpcklpd ymm1{k5}, ymm0, ymm2"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
@@ -946,6 +953,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x15, 0x0a], "vunpckhpd ymm1, ymm0, qword [rdx]{1to4}"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x15, 0x0a], "vunpckhpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0xca], "vunpckhpd ymm1{k5}{z}, ymm0, ymm2"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0xca]); // no broadcast in reg-reg
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0x0a], "vunpckhpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0xca], "vunpckhpd ymm1, ymm0, ymm2"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0xca], "vunpckhpd ymm1{k5}, ymm0, ymm2"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX
@@ -976,6 +984,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0xca], "vmovapd ymm1, ymm2"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0xca], "vmovapd ymm1{k5}, ymm2"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0x0a], "vmovapd ymm1, ymmword [rdx]"); // VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0x28, 0x0a]); // no broadcast
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0x0a], "vmovapd ymm1{k5}, ymmword [rdx]"); // VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0xca], "vmovapd zmm1{k5}{z}, zmm2"); // VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0x0a], "vmovapd zmm1{k5}{z}, zmmword [rdx]"); // VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -1008,6 +1017,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x2b, 0x0a], "vmovntpd zmmword [rdx], zmm1"); // VMOVNTPD_MEMf64_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x2b, 0x0a], "vmovntpd xmmword [rdx], xmm1"); // VMOVNTPD_MEMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2e, 0xca], "vucomisd xmm1{sae}, xmm2"); // VUCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x79, 0x2e, 0xca]); // mask reg must be 000
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0xca], "vucomisd xmm1, xmm2"); // VUCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0x0a], "vucomisd xmm1, qword [rdx]"); // VUCOMISD_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2f, 0xca], "vcomisd xmm1{sae}, xmm2"); // VCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
@@ -1289,6 +1299,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0xca], "vcvtps2dq ymm1{k5}{z}, ymm2"); // VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}{z}, ymmword [rdx]"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0xca], "vcvtps2dq ymm1, ymm2"); // VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x28, 0x5b, 0xca]); // no W=1
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0xca], "vcvtps2dq ymm1{k5}, ymm2"); // VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0x0a], "vcvtps2dq ymm1, ymmword [rdx]"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}, ymmword [rdx]"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
@@ -1563,6 +1574,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, dword [rdx]{1to8}"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0xca], "vpcmpgtd k1, ymm0, ymm2"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0xca], "vpcmpgtd k1{k5}, ymm0, ymm2"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0xca]); // no broadcast on reg operand (no sae)
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0x0a], "vpcmpgtd k1, ymm0, ymmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, ymmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x66, 0x0a], "vpcmpgtd k1, zmm0, dword [rdx]{1to16}"); // VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX
@@ -3218,16 +3230,21 @@ fn tests_66_0f() {
 fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0xca], "vmovss xmm1{k5}{z}, xmm0, xmm2"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0x0a], "vmovss xmm1{k5}{z}, dword [rdx]"); // VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6f, 0x10, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0xca], "vmovss xmm1, xmm0, xmm2"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0xca], "vmovss xmm1{k5}, xmm0, xmm2"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0x0a], "vmovss xmm1, dword [rdx]"); // VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x10, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0x0a], "vmovss xmm1{k5}, dword [rdx]"); // VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0xca], "vmovss xmm2{k5}{z}, xmm0, xmm1"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0xca], "vmovss xmm2, xmm0, xmm1"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0xca], "vmovss xmm2{k5}, xmm0, xmm1"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x3d, 0x11, 0xca]);
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0x0a], "vmovss dword [rdx], xmm1"); // VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0x0a], "vmovss dword [rdx]{k5}, xmm1"); // VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0xca], "vmovsldup ymm1{k5}{z}, ymm2"); // VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0x0a], "vmovsldup ymm1{k5}{z}, ymmword [rdx]"); // VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0xca], "vmovsldup ymm1, ymm2"); // VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0xca], "vmovsldup ymm1{k5}, ymm2"); // VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
@@ -3266,6 +3283,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2a, 0xca], "vcvtsi2ss xmm1{rz-sae}, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0xca], "vcvtsi2ss xmm1{rd-sae}, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2a, 0xca]); // mask reg must be 000
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0x0a], "vcvtsi2ss xmm1, xmm0, qword [rdx]"); // VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2a, 0xca], "vcvtsi2ss xmm1{rz-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x2a, 0xca], "vcvtsi2ss xmm1{rd-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
@@ -3277,6 +3295,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x2a, 0xca], "vcvtsi2ss xmm1{rne-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2c, 0xca], "vcvttss2si rcx{sae}, xmm2"); // VCVTTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0xca], "vcvttss2si rcx, xmm2"); // VCVTTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2c, 0xca]); // mask register must be 000
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0x0a], "vcvttss2si rcx, dword [rdx]"); // VCVTTSS2SI_GPR64i64_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2c, 0xca], "vcvttss2si ecx{sae}, xmm2"); // VCVTTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); // VCVTTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
@@ -3284,6 +3303,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2d, 0xca], "vcvtss2si rcx{rz-sae}, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0xca], "vcvtss2si rcx{rd-sae}, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0xca], "vcvtss2si rcx, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2d, 0xca]); // mask register must be 000
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0x0a], "vcvtss2si rcx, dword [rdx]"); // VCVTSS2SI_GPR64i64_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2d, 0xca], "vcvtss2si ecx{rz-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x2d, 0xca], "vcvtss2si ecx{rd-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
@@ -3349,6 +3369,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x59, 0xca], "vmulss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0xca], "vcvtss2sd xmm1{sae}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0x0a]); // no broadcast with memory source
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{sae}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0x0a], "vcvtss2sd xmm1{k5}{z}, xmm0, dword [rdx]"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -3699,6 +3720,8 @@ fn tests_f2_0f() {
 fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0xca], "vmovsd xmm1{k5}{z}, xmm0, xmm2"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0x0a], "vmovsd xmm1{k5}{z}, qword [rdx]"); // VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0x10, 0x0a]);
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x10, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0xca], "vmovsd xmm1, xmm0, xmm2"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0xca], "vmovsd xmm1{k5}, xmm0, xmm2"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0x0a], "vmovsd xmm1, qword [rdx]"); // VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -3706,10 +3729,13 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0xca], "vmovsd xmm2{k5}{z}, xmm0, xmm1"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0xca], "vmovsd xmm2, xmm0, xmm1"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0xca], "vmovsd xmm2{k5}, xmm0, xmm1"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x3d, 0x11, 0xca]);
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0x0a], "vmovsd qword [rdx], xmm1"); // VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0x0a], "vmovsd qword [rdx]{k5}, xmm1"); // VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0xca], "vmovddup ymm1{k5}{z}, ymm2"); // VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0x0a], "vmovddup ymm1{k5}{z}, ymmword [rdx]"); // VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x12, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0xca], "vmovddup ymm1, ymm2"); // VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0xca], "vmovddup ymm1{k5}, ymm2"); // VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0x0a], "vmovddup ymm1, ymmword [rdx]"); // VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -3763,6 +3789,8 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0xca], "vsqrtsd xmm1, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0xca], "vsqrtsd xmm1{k5}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0x0a], "vsqrtsd xmm1, xmm0, qword [rdx]"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x38, 0x51, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x51, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0x0a], "vsqrtsd xmm1{k5}, xmm0, qword [rdx]"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x51, 0xca], "vsqrtsd xmm1{ru-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
@@ -3814,6 +3842,8 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0x0a], "vcvtsd2ss xmm1{k5}{z}, xmm0, qword [rdx]"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x5a, 0x0a]); // no L'L=11 unless for sae
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x5a, 0x0a]); // no L'L=11 unless for sae
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0xca], "vcvtsd2ss xmm1, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0x0a], "vcvtsd2ss xmm1, xmm0, qword [rdx]"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
@@ -3871,6 +3901,7 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x5e, 0xca], "vdivsd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5f, 0xca], "vmaxsd xmm1{sae}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7f, 0x78, 0x5f, 0xca]); // requires W=1
     test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5f, 0xca], "vmaxsd xmm1{k5}{sae}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0x0a], "vmaxsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
@@ -4278,6 +4309,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0x0a], "vpsllvw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x13, 0xca], "vcvtph2ps zmm1{k5}{z}{sae}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x13, 0xca], "vcvtph2ps zmm1{sae}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x78, 0x13, 0x0a]); // W=0
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x13, 0xca], "vcvtph2ps zmm1{k5}{sae}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0xca], "vcvtph2ps ymm1{k5}{z}, xmm2"); // VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0x0a], "vcvtph2ps ymm1{k5}{z}, xmmword [rdx]"); // VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX
@@ -4310,6 +4342,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x14, 0x0a], "vprorvd ymm1, ymm0, dword [rdx]{1to8}"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x14, 0x0a], "vprorvd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0xca], "vprorvd ymm1{k5}{z}, ymm0, ymm2"); // VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0xca]); // no broadcast
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0x0a], "vprorvd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0xca], "vprorvd ymm1, ymm0, ymm2"); // VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0xca], "vprorvd ymm1{k5}, ymm0, ymm2"); // VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
@@ -4682,12 +4715,14 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0x0a], "vpmovsxwq xmm1, dword [rdx]"); // VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0x0a], "vpmovsxwq xmm1{k5}, dword [rdx]"); // VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0xca], "vpmovsxdq ymm1{k5}{z}, xmm2"); // VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x25, 0xca]); // W must be 1
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0x0a], "vpmovsxdq ymm1{k5}{z}, xmmword [rdx]"); // VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0xca], "vpmovsxdq ymm1, xmm2"); // VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0xca], "vpmovsxdq ymm1{k5}, xmm2"); // VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0x0a], "vpmovsxdq ymm1, xmmword [rdx]"); // VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0x0a], "vpmovsxdq ymm1{k5}, xmmword [rdx]"); // VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0xca], "vpmovsxdq zmm1{k5}{z}, ymm2"); // VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xcd, 0x25, 0xca]);
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0x0a], "vpmovsxdq zmm1{k5}{z}, ymmword [rdx]"); // VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0xca], "vpmovsxdq zmm1, ymm2"); // VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0xca], "vpmovsxdq zmm1{k5}, ymm2"); // VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX
@@ -4703,10 +4738,12 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0xca], "vptestmw k1{k5}, ymm0, ymm2"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0x0a], "vptestmw k1, ymm0, ymmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0x0a], "vptestmw k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x26, 0x0a]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0xca], "vptestmb k1, ymm0, ymm2"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0xca], "vptestmb k1{k5}, ymm0, ymm2"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0x0a], "vptestmb k1, ymm0, ymmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0x0a], "vptestmb k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x26, 0x0a]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0xca], "vptestmw k1, zmm0, zmm2"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0xca], "vptestmw k1{k5}, zmm0, zmm2"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0x0a], "vptestmw k1, zmm0, zmmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX
@@ -4731,12 +4768,15 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0x0a], "vptestmq k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x27, 0x0a], "vptestmd k1, ymm0, dword [rdx]{1to8}"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, dword [rdx]{1to8}"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xdd, 0x27, 0x0a]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0xca], "vptestmd k1, ymm0, ymm2"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0xca], "vptestmd k1{k5}, ymm0, ymm2"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0xca]); // no invalid broadcast mode
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0x0a], "vptestmd k1, ymm0, ymmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x27, 0x0a], "vptestmq k1, zmm0, qword [rdx]{1to8}"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x27, 0x0a], "vptestmq k1{k5}, zmm0, qword [rdx]{1to8}"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xdd, 0x27, 0x0a]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x27, 0x0a], "vptestmq k1, xmm0, qword [rdx]{1to2}"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x27, 0x0a], "vptestmq k1{k5}, xmm0, qword [rdx]{1to2}"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0xca], "vptestmq k1, zmm0, zmm2"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX
@@ -4763,6 +4803,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x28, 0x0a], "vpmuldq ymm1, ymm0, qword [rdx]{1to4}"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x28, 0x0a], "vpmuldq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0xca], "vpmuldq ymm1{k5}{z}, ymm0, ymm2"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0xca]); // no broadcast on register source
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0x0a], "vpmuldq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0xca], "vpmuldq ymm1, ymm0, ymm2"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0xca], "vpmuldq ymm1{k5}, ymm0, ymm2"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX
@@ -4790,6 +4831,8 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, qword [rdx]{1to4}"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0xca], "vpcmpeqq k1, ymm0, ymm2"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0xca], "vpcmpeqq k1{k5}, ymm0, ymm2"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x29, 0xca]); // no zero-merge
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0xca]); // no zero-merge
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0x0a], "vpcmpeqq k1, ymm0, ymmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, ymmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x29, 0x0a], "vpcmpeqq k1, zmm0, qword [rdx]{1to8}"); // VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX
@@ -4925,6 +4968,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0x0a], "vscalefsd xmm1, xmm0, qword [rdx]"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0x0a], "vscalefsd xmm1{k5}, xmm0, qword [rdx]"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0x0a]); // sae is indicated by evex.b, with memory source evex.b implies broadcast as well. vscalefss does not broadcast, so reject.
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x2d, 0xca], "vscalefss xmm1{rz-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x2d, 0xca], "vscalefss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
@@ -5526,6 +5570,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x43, 0xca], "vgetexpss xmm1{k5}{sae}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0xca], "vgetexpss xmm1{k5}{z}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0x0a], "vgetexpss xmm1{k5}{z}, xmm0, dword [rdx]"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x43, 0x0a]); // no broadcast
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0xca], "vgetexpss xmm1, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0xca], "vgetexpss xmm1{k5}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0x0a], "vgetexpss xmm1, xmm0, dword [rdx]"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -5810,6 +5855,8 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0x0a], "vrcp14ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0xca], "vrcp14ss xmm1, xmm0, xmm2"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0xca], "vrcp14ss xmm1{k5}, xmm0, xmm2"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4d, 0xca]); // no sae
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x6d, 0x4d, 0xca]); // no L'L=11
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0x0a], "vrcp14ss xmm1, xmm0, dword [rdx]"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0x0a], "vrcp14ss xmm1{k5}, xmm0, dword [rdx]"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}{z}, qword [rdx]{1to4}"); // VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -5828,6 +5875,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}{z}, ymmword [rdx]"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0xca], "vrsqrt14ps ymm1, ymm2"); // VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0xca], "vrsqrt14ps ymm1{k5}, ymm2"); // VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0xca]); // no sae
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0x0a], "vrsqrt14ps ymm1, ymmword [rdx]"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}, ymmword [rdx]"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}{z}, qword [rdx]{1to8}"); // VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX
@@ -5875,6 +5923,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}{z}, xmm0, xmm2"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0xca], "vrsqrt14ss xmm1, xmm0, xmm2"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x68, 0x4f, 0xca]); // no L'L=11
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}, xmm0, xmm2"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0x0a], "vrsqrt14ss xmm1, xmm0, dword [rdx]"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}, xmm0, dword [rdx]"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -6194,6 +6243,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0xca], "vpcompressb ymm2{k5}, ymm1"); // VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0x0a], "vpcompressb ymmword [rdx], ymm1"); // VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0x0a], "vpcompressb ymmword [rdx]{k5}, ymm1"); // VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x63, 0x0a]); // no zero-merge on memory operands
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x63, 0xca], "vpcompressw zmm2{k5}{z}, zmm1"); // VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0xca], "vpcompressw zmm2, zmm1"); // VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0xca], "vpcompressw zmm2{k5}, zmm1"); // VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
@@ -6649,6 +6699,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0xca], "vpbroadcastb ymm1{k5}{z}, xmm2"); // VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0x0a], "vpbroadcastb ymm1{k5}{z}, byte [rdx]"); // VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0xca], "vpbroadcastb ymm1, xmm2"); // VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x78, 0xca]); // deny evex.b
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0xca], "vpbroadcastb ymm1{k5}, xmm2"); // VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0x0a], "vpbroadcastb ymm1, byte [rdx]"); // VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0x0a], "vpbroadcastb ymm1{k5}, byte [rdx]"); // VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX
@@ -6684,6 +6735,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0x0a], "vpbroadcastw xmm1{k5}, word [rdx]"); // VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7a, 0xca], "vpbroadcastb ymm1{k5}{z}, edx"); // VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7a, 0xca], "vpbroadcastb ymm1, edx"); // VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7a, 0xca]); // still no evex.b
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7a, 0xca], "vpbroadcastb ymm1{k5}, edx"); // VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7a, 0xca], "vpbroadcastb zmm1{k5}{z}, edx"); // VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7a, 0xca], "vpbroadcastb zmm1, edx"); // VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX
@@ -6705,6 +6757,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7c, 0xca], "vpbroadcastq ymm1{k5}, rdx"); // VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7c, 0xca], "vpbroadcastd ymm1{k5}{z}, edx"); // VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7c, 0xca], "vpbroadcastd ymm1, edx"); // VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7c, 0xca]); // no broadcast here either
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7c, 0xca], "vpbroadcastd ymm1{k5}, edx"); // VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7c, 0xca], "vpbroadcastq zmm1{k5}{z}, rdx"); // VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7c, 0xca], "vpbroadcastq zmm1, rdx"); // VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX
@@ -9171,6 +9224,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0xca], "vpmovuswb xmm2{k5}, ymm1"); // VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0x0a], "vpmovuswb xmmword [rdx], ymm1"); // VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0x0a], "vpmovuswb xmmword [rdx]{k5}, ymm1"); // VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xad, 0x10, 0x0a]); // cannot set evex.z on stores.
     test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x10, 0xca], "vpmovuswb ymm2{k5}{z}, zmm1"); // VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0xca], "vpmovuswb ymm2, zmm1"); // VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0xca], "vpmovuswb ymm2{k5}, zmm1"); // VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
@@ -9206,6 +9260,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0xca], "vpmovusqb xmm2{k5}, zmm1"); // VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0x0a], "vpmovusqb qword [rdx], zmm1"); // VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0x0a], "vpmovusqb qword [rdx]{k5}, zmm1"); // VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xcd, 0x12, 0x0a]);
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, xmm1"); // VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0xca], "vpmovusqb xmm2, xmm1"); // VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0xca], "vpmovusqb xmm2{k5}, xmm1"); // VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX
@@ -9557,6 +9612,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x72, 0x0a], "vcvtneps2bf16 xmm1, dword [rdx]{1to8}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, dword [rdx]{1to8}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}{z}, ymm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0xca]); // no register-register broadcast
     test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, ymmword [rdx]"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0xca], "vcvtneps2bf16 xmm1, ymm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}, ymm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
@@ -9585,6 +9641,8 @@ fn tests_f2_0f38() {
 fn tests_f3_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0x0a], "vp2intersectd k1, xmm0, xmmword [rdx]"); // VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); // VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX
+    test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); // VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7f, 0x09, 0x68, 0xca]); // requires mask reg to be 000
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1, xmm0, xmmword [rdx]"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0xca], "vcvtne2ps2bf16 xmm1, xmm0, xmm2"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmmword [rdx]"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX
@@ -9639,6 +9697,7 @@ fn tests_f3_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7f, 0xdd, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0x0a], "vp2intersectq k1, xmm0, xmmword [rdx]"); // VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0xca], "vp2intersectq k1, xmm0, xmm2"); // VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xff, 0x09, 0x68, 0xca]); // requires mask reg to be 000
     test_avx_full(&[0x62, 0xf2, 0xff, 0x18, 0x68, 0x0a], "vp2intersectq k1, xmm0, qword [rdx]{1to2}"); // VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0x0a], "vp2intersectq k1, ymm0, ymmword [rdx]"); // VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0xca], "vp2intersectq k1, ymm0, ymm2"); // VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX