even more EVEX encoding precision, regspec constructors are const

6 files changed, 267 insertions, 107 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 40e8e5a..7ed3def 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -7,6 +7,8 @@
     even when their corresponding extension is not selected.
 * added uarch-specific decoders for Zen 2, Zen 3, Zen 4, and Zen 5
 * removed 3DNow support from AMD uarch-specific decoders after K10
+* RegSpec register helpers to construct RegSpec from register numbers are now const fn
+  (RegSpec::xmm, RegSpec::q, RegSpec::d, RegSpec::st, etc)
 * for uarch-specific decoding, there is now a feature bit for Intel Key Locker. this corrects an
   issue where Key Locker instructions would decode under AMD-specific decoders.
 * push-immediate, pushf, popf, leave, and xlat now all report a correct memory
diff --git a/src/isa_settings.rs b/src/isa_settings.rs
index 20d2e3f..96233f3 100644
--- a/src/isa_settings.rs
+++ b/src/isa_settings.rs
@@ -91,6 +91,20 @@ macro_rules! gen_isa_settings {
             Opcode::VP4DPWSSD,
         ];
 
+        // only present in Knights *?
+        static AVX512_ER: &[Opcode] = &[
+            Opcode::VEXP2PD,
+            Opcode::VEXP2PS,
+            Opcode::VRCP28PD,
+            Opcode::VRCP28PS,
+            Opcode::VRCP28SD,
+            Opcode::VRCP28SS,
+            Opcode::VRSQRT28PD,
+            Opcode::VRSQRT28PS,
+            Opcode::VRSQRT28SD,
+            Opcode::VRSQRT28SS,
+        ];
+
         /// optionally reject or reinterpret instruction according to settings for this decode
         /// operation.
         pub(crate) fn revise_instruction(settings: &$featureful_decoder, inst: &mut $inst_ty) -> Result<(), $decode_err> {
@@ -113,6 +127,8 @@ macro_rules! gen_isa_settings {
                         return Err(<$decode_err>::InvalidOpcode);
                     } else if !settings.avx512_4fmaps() && AVX512_4FMAPS.contains(&inst.opcode) {
                         return Err(<$decode_err>::InvalidOpcode);
+                    } else if !settings.avx512_er() && AVX512_ER.contains(&inst.opcode) {
+                        return Err(<$decode_err>::InvalidOpcode);
                     } else if avx512_baseline {
                         // TODO: hack around missing avx feature set specificity.
                         return Ok(());
@@ -823,6 +839,11 @@ macro_rules! gen_isa_settings {
                         return Err(<$decode_err>::InvalidOpcode);
                     }
                 }
+                <$opcode>::HRESET => {
+                    if !settings.hreset() {
+                        return Err(<$decode_err>::InvalidOpcode);
+                    }
+                }
 
                 other => {
                     if !settings.bmi1() {
@@ -997,6 +1018,7 @@ macro_rules! gen_arch_isa_settings {
             avx512_ifma, with_avx512_ifma = 110;
 
             keylocker, with_keylocker = 111;
+            hreset, with_hreset = 112;
 
             {
                 sse4 = {
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 4165885..1b5caf1 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -135,10 +135,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for x87 register `st(num)`
     #[inline]
-    pub fn st(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x87 reg st({})", num);
-        }
+    pub const fn st(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x87 reg");
 
         RegSpec {
             num,
@@ -148,10 +146,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for xmm reg `num`
     #[inline]
-    pub fn xmm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 xmm reg {}", num);
-        }
+    pub const fn xmm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 xmm reg");
 
         RegSpec {
             num,
@@ -161,10 +157,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for ymm reg `num`
     #[inline]
-    pub fn ymm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 ymm reg {}", num);
-        }
+    pub const fn ymm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 ymm reg");
 
         RegSpec {
             num,
@@ -174,10 +168,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for zmm reg `num`
     #[inline]
-    pub fn zmm(num: u8) -> RegSpec {
-        if num >= 32 {
-            panic!("invalid x86 zmm reg {}", num);
-        }
+    pub const fn zmm(num: u8) -> RegSpec {
+        assert!(num < 32, "invalid x86 zmm reg");
 
         RegSpec {
             num,
@@ -187,10 +179,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for qword reg `num`
     #[inline]
-    pub fn q(num: u8) -> RegSpec {
-        if num >= 16 {
-            panic!("invalid x86 qword reg {}", num);
-        }
+    pub const fn q(num: u8) -> RegSpec {
+        assert!(num < 16, "invalid x86 qword reg");
 
         RegSpec {
             num,
@@ -200,10 +190,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for mask reg `num`
     #[inline]
-    pub fn mask(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 mask reg {}", num);
-        }
+    pub const fn mask(num: u8) -> RegSpec {
+        assert!(num < 8, "invalid x86 mask reg");
 
         RegSpec {
             num,
@@ -213,10 +201,8 @@ impl RegSpec {
 
     /// construct a `RegSpec` for dword reg `num`
     #[inline]
-    pub fn d(num: u8) -> RegSpec {
-        if num >= 16 {
-            panic!("invalid x86 dword reg {}", num);
-        }
+    pub const fn d(num: u8) -> RegSpec {
+        assert!(num < 16, "invalid x86 dword reg");
 
         RegSpec {
             num,
@@ -227,9 +213,7 @@ impl RegSpec {
     /// construct a `RegSpec` for word reg `num`
     #[inline]
     pub fn w(num: u8) -> RegSpec {
-        if num >= 16 {
-            panic!("invalid x86 word reg {}", num);
-        }
+        assert!(num < 16, "invalid x86 word reg");
 
         RegSpec {
             num,
@@ -240,9 +224,7 @@ impl RegSpec {
     /// construct a `RegSpec` for non-rex byte reg `num`
     #[inline]
     pub fn rb(num: u8) -> RegSpec {
-        if num >= 16 {
-            panic!("invalid x86 rex-byte reg {}", num);
-        }
+        assert!(num < 16, "invalid x86 rex-byte reg");
 
         let bank = if num < 4 {
             RegisterBank::B
@@ -259,9 +241,7 @@ impl RegSpec {
     /// construct a `RegSpec` for non-rex byte reg `num`
     #[inline]
     pub fn b(num: u8) -> RegSpec {
-        if num >= 8 {
-            panic!("invalid x86 non-rex byte reg {}", num);
-        }
+        assert!(num < 8, "invalid x86 non-rex-byte reg");
 
         RegSpec {
             num,
diff --git a/src/shared/evex.in b/src/shared/evex.in
index a15b59b..07c82e5 100644
--- a/src/shared/evex.in
+++ b/src/shared/evex.in
@@ -572,7 +572,10 @@ pub(crate) fn read_evex_operands<
           instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
         }
       } else {
-        if instruction.prefixes.evex_unchecked().broadcast() {
+        deny_broadcast(instruction)?;
+
+        if instruction.prefixes.evex_unchecked().lp() &&
+          instruction.prefixes.evex_unchecked().vex().l() {
           return Err(DecodeError::InvalidOpcode);
         }
 
@@ -781,6 +784,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::G_V_Ed_xmm_imm8_W0 => {
       deny_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -827,6 +832,9 @@ pub(crate) fn read_evex_operands<
           return Err(DecodeError::InvalidOperand);
         }
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       instruction.operands[1] = OperandSpec::RegVex;
@@ -835,6 +843,8 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::G_V_xmm_Edq_imm8 => {
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let (sz, bank) = if instruction.prefixes.evex_unchecked().vex().w() {
         if isa_has_qwords() {
@@ -865,6 +875,8 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::G_V_xmm_Ebd_imm8 => {
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -925,28 +937,12 @@ pub(crate) fn read_evex_operands<
 
       set_reg_sizes_from_ll(instruction)?;
     }
-    generated::EVEXOperandCode::M_G_LL_W0 => {
-      deny_vex_reg(instruction)?;
-      deny_mask_reg(instruction)?;
-
-      instruction.mem_size = regs_size(instruction);
-
-      let modrm = read_modrm(words)?;
-      set_rrr(instruction, modrm);
-      let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
-      if mem_oper == OperandSpec::RegMMM {
-        return Err(DecodeError::InvalidOperand);
-      }
-      instruction.operands[0] = mem_oper;
-      instruction.operands[1] = OperandSpec::RegRRR;
-      instruction.operand_count = 2;
-
-      set_reg_sizes_from_ll(instruction)?;
-    }
     generated::EVEXOperandCode::M_G_LL_W1 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
@@ -983,6 +979,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::G_Ed_xmm_sae_W0 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
       // vucomiss and vcomiss both are W=0
       ensure_W(instruction, 0)?;
 
@@ -991,12 +988,18 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       instruction.regs[0].bank = RegisterBank::X;
 
       // in specific support of vcomisd/vucomisd
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       instruction.operands[1] = mem_oper;
@@ -1005,6 +1008,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Gm_Eq_xmm_sae_W1 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
       // vucomisd and vcomisd both are W=1
       ensure_W(instruction, 1)?;
 
@@ -1013,12 +1017,18 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       instruction.regs[0].bank = RegisterBank::X;
 
       // in specific support of vcomisd/vucomisd
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       instruction.operands[1] = mem_oper;
@@ -1097,6 +1107,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Maskm_V_E_LL_imm8_sae_bcast_W1 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 1)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -1389,9 +1400,8 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::G_V_E_LL => {
       deny_mask_reg(instruction)?;
-      if [Opcode::VAESDECLAST, Opcode::VAESDEC, Opcode::VAESENC, Opcode::VAESENCLAST].contains(&instruction.opcode) {
-        deny_z(instruction)?;
-      }
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -1490,6 +1500,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = mem_oper;
       instruction.imm = read_imm_unsigned(words, 1)?;
@@ -1510,6 +1523,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = mem_oper;
       instruction.imm = read_imm_unsigned(words, 1)?;
@@ -1734,6 +1750,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         if instruction.prefixes.evex_unchecked().broadcast() {
           // sae sets this to `vcvtps2ph ymm, zmm, imm8`
@@ -1767,6 +1784,7 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         if instruction.prefixes.evex_unchecked().broadcast() {
           // sae sets this to `vcvtps2ph ymm, zmm, imm8`
@@ -1801,6 +1819,7 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       instruction.regs[0].bank = RegisterBank::Z;
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       if mem_oper == OperandSpec::RegMMM {
         if instruction.prefixes.evex_unchecked().broadcast() {
           instruction.operands[0] = OperandSpec::RegMMM_maskmerge_sae_noround;
@@ -1808,6 +1827,9 @@ pub(crate) fn read_evex_operands<
           instruction.operands[0] = OperandSpec::RegMMM_maskmerge;
         }
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         if instruction.prefixes.evex_unchecked().broadcast() {
           return Err(DecodeError::InvalidOperand);
         } else {
@@ -1916,6 +1938,7 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       instruction.regs[0].bank = RegisterBank::Z;
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.mem_size = 32;
       instruction.operands[0] = mem_oper.masked();
       instruction.operands[1] = OperandSpec::RegRRR;
@@ -2488,6 +2511,7 @@ pub(crate) fn read_evex_operands<
         instruction.regs[0].bank = RegisterBank::Y;
       }
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      check_allowed_zero_merge(&instruction.prefixes, mem_oper)?;
       instruction.mem_size = 16;
       instruction.operands[0] = mem_oper.masked();
       instruction.operands[1] = OperandSpec::RegRRR;
@@ -2614,32 +2638,12 @@ pub(crate) fn read_evex_operands<
       instruction.operands[3] = OperandSpec::ImmU8;
       instruction.operand_count = 4;
     }
-    generated::EVEXOperandCode::VMOVQ_G_Ed_xmm => {
-      deny_mask_reg(instruction)?;
-      deny_vex_reg(instruction)?;
-      ensure_W(instruction, 1)?;
-      deny_broadcast(instruction)?;
-
-      let modrm = read_modrm(words)?;
-      set_rrr(instruction, modrm);
-      instruction.regs[0].bank = RegisterBank::X;
-      let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
-
-      if mem_oper == OperandSpec::RegMMM {
-        instruction.mem_size = 0;
-      } else {
-        instruction.mem_size = 8;
-      }
-
-      instruction.operands[0] = OperandSpec::RegRRR;
-      instruction.operands[1] = mem_oper;
-      instruction.operand_count = 2;
-    }
     generated::EVEXOperandCode::VMOVQ_Ed_G_xmm => {
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 1)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2661,6 +2665,7 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 1)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2679,6 +2684,7 @@ pub(crate) fn read_evex_operands<
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2710,6 +2716,7 @@ pub(crate) fn read_evex_operands<
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -2878,6 +2885,7 @@ pub(crate) fn read_evex_operands<
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2913,6 +2921,7 @@ pub(crate) fn read_evex_operands<
       deny_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2948,6 +2957,7 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 1)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2975,6 +2985,7 @@ pub(crate) fn read_evex_operands<
       deny_vex_reg(instruction)?;
       ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -2997,10 +3008,11 @@ pub(crate) fn read_evex_operands<
         return Err(DecodeError::InvalidOperand);
       }
     }
-    generated::EVEXOperandCode::G_E_LL_W0 => {
+    generated::EVEXOperandCode::G_M_LL_W0 => {
       deny_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3010,7 +3022,7 @@ pub(crate) fn read_evex_operands<
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if mem_oper == OperandSpec::RegMMM {
-        instruction.mem_size = 0;
+        return Err(DecodeError::InvalidOperand);
       }
       instruction.operands[0] = OperandSpec::RegRRR;
       instruction.operands[1] = mem_oper;
@@ -3018,20 +3030,20 @@ pub(crate) fn read_evex_operands<
 
       set_reg_sizes_from_ll(instruction)?;
     }
-    generated::EVEXOperandCode::E_G_LL_W0 => {
+    generated::EVEXOperandCode::M_G_LL_W0 => {
+      deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
-      let sz = regs_size(instruction);
-
-      instruction.mem_size = sz;
+      instruction.mem_size = regs_size(instruction);
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if mem_oper == OperandSpec::RegMMM {
-        instruction.mem_size = 0;
+        return Err(DecodeError::InvalidOperand);
       }
       instruction.operands[0] = mem_oper;
       instruction.operands[1] = OperandSpec::RegRRR;
@@ -3688,6 +3700,10 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp()
+          && instruction.prefixes.evex_unchecked().vex().l() {
+            return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       }
       instruction.operands[1] = OperandSpec::RegVex;
@@ -3720,6 +3736,10 @@ pub(crate) fn read_evex_operands<
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp()
+          && instruction.prefixes.evex_unchecked().vex().l() {
+            return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       }
       instruction.operands[1] = OperandSpec::RegVex;
@@ -3738,6 +3758,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL_imm8 => {
       check_mask_reg(instruction)?;
       deny_broadcast(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
       instruction.mem_size = sz;
@@ -3812,6 +3833,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_E_LL_imm8_bcast => {
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3857,6 +3879,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Mask_V_E_LL_imm8_sae_bcast_W0 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3903,6 +3926,7 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Mask_V_E_LL_imm8_bcast => {
       check_mask_reg(instruction)?;
+      deny_z(instruction)?;
 
       let sz = regs_size(instruction);
 
@@ -3984,6 +4008,9 @@ pub(crate) fn read_evex_operands<
       apply_broadcast(instruction, item_size, sz);
 
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegVex_maskmerge;
       instruction.operands[1] = mem_oper;
       instruction.imm = read_imm_unsigned(words, 1)?;
@@ -4072,17 +4099,14 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Gm_V_E_LL_imm8_W0 => {
       check_mask_reg(instruction)?;
       ensure_W(instruction, 0)?;
+      deny_broadcast(instruction)?;
 
       let sz = regs_size(instruction);
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
-      if mem_oper == OperandSpec::RegMMM {
-        deny_broadcast(instruction)?;
-      } else {
-        instruction.mem_size = sz;
-      }
+      instruction.mem_size = sz;
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
@@ -4107,6 +4131,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
@@ -4117,7 +4144,9 @@ pub(crate) fn read_evex_operands<
       set_reg_sizes_from_ll(instruction)?;
     }
     generated::EVEXOperandCode::G_V_E_LL_imm8 => {
-      check_mask_reg(instruction)?;
+      deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
@@ -4135,6 +4164,7 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Gm_V_E_LL_imm8 => {
       check_mask_reg(instruction)?;
+      deny_broadcast(instruction)?;
 
       instruction.mem_size = regs_size(instruction);
 
@@ -4161,6 +4191,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper == OperandSpec::RegMMM {
+        deny_broadcast(instruction)?;
+      }
       instruction.operands[0] = OperandSpec::RegRRR_maskmerge;
       instruction.operands[1] = OperandSpec::RegVex;
       instruction.operands[2] = mem_oper;
@@ -4537,6 +4570,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VCVTTPD2DQ => {
       check_mask_reg(instruction)?;
       deny_vex_reg(instruction)?;
+      ensure_W(instruction, 1)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4780,6 +4814,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Edd_G_xmm_imm8 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4841,6 +4877,9 @@ pub(crate) fn read_evex_operands<
           }
         }
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         if instruction.prefixes.evex_unchecked().broadcast() {
           return Err(DecodeError::InvalidOpcode);
         }
@@ -4855,6 +4894,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::VEXTRACTPS => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4875,6 +4916,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Ewd_G_xmm_imm8 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4895,6 +4938,8 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Ebd_G_xmm_imm8 => {
       deny_vex_reg(instruction)?;
       deny_mask_reg(instruction)?;
+      deny_z(instruction)?;
+      deny_broadcast(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
@@ -4947,6 +4992,10 @@ pub(crate) fn read_evex_operands<
       if let OperandSpec::RegMMM = mem_oper {
         instruction.mem_size = 0;
       } else{
+        deny_broadcast(instruction)?;
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.mem_size = item_size;
       }
       if instruction.prefixes.evex_unchecked().broadcast() {
@@ -4964,13 +5013,18 @@ pub(crate) fn read_evex_operands<
     }
     generated::EVEXOperandCode::Gm_V_E_xmm_imm8_sae_W1 => {
       ensure_W(instruction, 1)?;
+      check_mask_reg(instruction)?;
 
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
       if let OperandSpec::RegMMM = mem_oper {
         /* no mem size */
-      } else{
+      } else {
+        deny_broadcast(instruction)?;
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.mem_size = 8;
       }
       if instruction.prefixes.evex_unchecked().broadcast() {
@@ -5126,6 +5180,9 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       if instruction.prefixes.evex_unchecked().broadcast() && mem_oper == OperandSpec::RegMMM {
         if (!instruction.prefixes.evex_unchecked().vex().w() || !isa_has_qwords()) && instruction.opcode == Opcode::VCVTSI2SD {
           instruction.operands[0] = OperandSpec::RegRRR;
@@ -5133,6 +5190,9 @@ pub(crate) fn read_evex_operands<
           instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
         }
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       instruction.operands[1] = OperandSpec::RegVex;
@@ -5171,9 +5231,15 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround;
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       if instruction.prefixes.evex_unchecked().vex().w() {
@@ -5198,9 +5264,15 @@ pub(crate) fn read_evex_operands<
       let modrm = read_modrm(words)?;
       set_rrr(instruction, modrm);
       let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?;
+      if mem_oper.is_memory() {
+        deny_broadcast(instruction)?;
+      }
       if instruction.prefixes.evex_unchecked().broadcast() {
         instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae;
       } else {
+        if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() {
+          return Err(DecodeError::InvalidOpcode);
+        }
         instruction.operands[0] = OperandSpec::RegRRR;
       }
       if instruction.prefixes.evex_unchecked().vex().w() {
@@ -5221,6 +5293,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Operands_12_W0 => {
       deny_mask_reg(instruction)?;
       deny_z(instruction)?;
+      deny_broadcast(instruction)?;
       ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
@@ -5246,6 +5319,7 @@ pub(crate) fn read_evex_operands<
     generated::EVEXOperandCode::Operands_16_W0 => {
       deny_mask_reg(instruction)?;
       deny_z(instruction)?;
+      deny_broadcast(instruction)?;
       ensure_W(instruction, 0)?;
 
       let modrm = read_modrm(words)?;
diff --git a/src/shared/generated_evex.in b/src/shared/generated_evex.in
index f2ccc76..3f3764b 100644
--- a/src/shared/generated_evex.in
+++ b/src/shared/generated_evex.in
@@ -506,7 +506,6 @@ pub(crate) enum EVEXOperandCode {
   Gm_U_zmm_imm8_sae_W0,
   Gm_V_E_LL_sae_W1,
   Gm_U_zmm_sae_W0,
-  E_G_LL_W0,
   Ebd_G_xmm_imm8,
   Edd_G_xmm_imm8,
   Edm_xmm_G_xmm_W0,
@@ -527,7 +526,7 @@ pub(crate) enum EVEXOperandCode {
   Eqm_xmm_G_zmm_W0,
   Ewd_G_xmm_imm8,
   Ewm_xmm_G_xmm_W0,
-  G_E_LL_W0,
+  G_M_LL_W0,
   G_Ed_xmm_sae_W0,
   G_LL_Mask,
   G_LL_Mask_W0,
@@ -667,7 +666,6 @@ pub(crate) enum EVEXOperandCode {
   VMOVD_7e,
   VMOVQ_7e,
   VMOVQ_Ed_G_xmm,
-  VMOVQ_G_Ed_xmm,
   VMOVSD_10,
   VMOVSD_11,
   VMOVSS_10,
@@ -676,15 +674,23 @@ pub(crate) enum EVEXOperandCode {
   VPINSRW,
 }
 
+// the APM and SDM describe the prefix bits as selecting no prefix, "66, f2, or f3" opcode extension.
+// however, this is *not the order those bits are interpreted in*. compare APM and SDM encodings and
+// you will see:
+// > 0b00 -> none,
+// > 0b01 -> 0x66,
+// > 0b10 -> 0xf3, // !!
+// > 0b11 -> 0xf2, // !!
+// hence the ordering of table names below.
 pub(crate) const TABLES: [&'static [(u8, [(super::Opcode, EVEXOperandCode); 4])]; 12] = [
   &EVEX_None_0f,
   &EVEX_66_0f,
-  &EVEX_f2_0f,
   &EVEX_f3_0f,
+  &EVEX_f2_0f,
   &DUMMY,
   &EVEX_66_0f38,
-  &EVEX_f2_0f38,
   &EVEX_f3_0f38,
+  &EVEX_f2_0f38,
   &DUMMY,
   &EVEX_66_0f3a,
   &DUMMY,
@@ -807,7 +813,7 @@ const EVEX_66_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 100] = [
   (0xe4, [(super::Opcode::VPMULHUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xe5, [(super::Opcode::VPMULHW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xe6, [(super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ)]),
-  (0xe7, [(super::Opcode::VMOVNTDQ, EVEXOperandCode::E_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::E_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::E_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0xe7, [(super::Opcode::VMOVNTDQ, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::M_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xe8, [(super::Opcode::VPSUBSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xe9, [(super::Opcode::VPSUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xea, [(super::Opcode::VPMINSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -862,7 +868,7 @@ const EVEX_66_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 143] = [
   (0x27, [(super::Opcode::VPTESTMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VPTESTMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VPTESTMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x28, [(super::Opcode::VPMULDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x29, [(super::Opcode::VPCMPEQQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::VPCMPEQQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::VPCMPEQQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x2a, [(super::Opcode::VMOVNTDQA, EVEXOperandCode::G_E_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_E_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
+  (0x2a, [(super::Opcode::VMOVNTDQA, EVEXOperandCode::G_M_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_M_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_M_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2b, [(super::Opcode::VPACKUSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPACKUSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPACKUSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x2c, [(super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]),
   (0x2d, [(super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae)]),
@@ -1022,7 +1028,7 @@ const EVEX_66_0f3a: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 51] = [
   (0x56, [(super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae), (super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae), (super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae), (super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae)]),
   (0x57, [(super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae)]),
   (0x66, [(super::Opcode::VFPCLASSPS, EVEXOperandCode::Mask_E_LL_imm8_bcast), (super::Opcode::VFPCLASSPS, EVEXOperandCode::Mask_E_LL_imm8_bcast), (super::Opcode::VFPCLASSPS, EVEXOperandCode::Mask_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
-  (0x67, [(super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8)]),
+  (0x67, [(super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x70, [(super::Opcode::VPSHLDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHLDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHLDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x71, [(super::Opcode::VPSHLDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPSHLDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPSHLDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x72, [(super::Opcode::VPSHRDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHRDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHRDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -1031,7 +1037,7 @@ const EVEX_66_0f3a: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 51] = [
   (0xcf, [(super::Opcode::VGF2P8AFFINEINVQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VGF2P8AFFINEINVQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VGF2P8AFFINEINVQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
 ];
 
-const EVEX_f2_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 26] = [
+const EVEX_f3_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 26] = [
   (0x10, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W0
   (0x11, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W0
   (0x12, [(super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -1060,7 +1066,7 @@ const EVEX_f2_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 26] = [
   (0xe6, [(super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD)]),
 ];
 
-const EVEX_f2_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 28] = [
+const EVEX_f3_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 28] = [
   (0x10, [(super::Opcode::VPMOVUSWB, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSWB, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVUSWB, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x11, [(super::Opcode::VPMOVUSDB, EVEXOperandCode::Edm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSDB, EVEXOperandCode::Eqm_xmm_G_ymm_W0), (super::Opcode::VPMOVUSDB, EVEXOperandCode::Em_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x12, [(super::Opcode::VPMOVUSQB, EVEXOperandCode::Ewm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSQB, EVEXOperandCode::Edm_xmm_G_ymm_W0), (super::Opcode::VPMOVUSQB, EVEXOperandCode::Eqm_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -1091,7 +1097,7 @@ const EVEX_f2_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 28] = [
   (0x72, [(super::Opcode::VCVTNEPS2BF16, EVEXOperandCode::Operands_72_W0), (super::Opcode::VCVTNEPS2BF16, EVEXOperandCode::Operands_72_W0), (super::Opcode::VCVTNEPS2BF16, EVEXOperandCode::Operands_72_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
 ];
 
-const EVEX_f3_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 24] = [
+const EVEX_f2_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 23] = [
   (0x10, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W1
   (0x11, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),// W1
   (0x12, [(super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
@@ -1112,13 +1118,12 @@ const EVEX_f3_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 24] = [
   (0x79, [(super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae)]),
   (0x7a, [(super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS)]),
   (0x7b, [(super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD), (super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD), (super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD), (super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD)]),
-  (0x7e, [(super::Opcode::VMOVQ, EVEXOperandCode::VMOVQ_G_Ed_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x7f, [(super::Opcode::VMOVDQU8, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Em_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0xc2, [(super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1), (super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1), (super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1), (super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1)]),
   (0xe6, [(super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ)]),
 ];
 
-const EVEX_f3_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 8] = [
+const EVEX_f2_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 8] = [
   (0x52, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VP4DPWSSD, EVEXOperandCode::Gm_V_zmm_M_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x53, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VP4DPWSSDS, EVEXOperandCode::Gm_V_zmm_M_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
   (0x68, [(super::Opcode::VP2INTERSECTD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VP2INTERSECTD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VP2INTERSECTD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]),
diff --git a/test/long_mode/evex_generated.rs b/test/long_mode/evex_generated.rs
index 48ab803..93dd69e 100644
--- a/test/long_mode/evex_generated.rs
+++ b/test/long_mode/evex_generated.rs
@@ -120,6 +120,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x0a], "vmovups xmmword [rdx]{k5}, xmm1"); // VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX
     test_invalid(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0x0a]);
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0xca], "vmovhlps xmm1, xmm0, xmm2"); // VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x12, 0xca]); // no broadcast
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x0a], "vmovlps xmm1, xmm0, qword [rdx]"); // VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x13, 0x0a], "vmovlps qword [rdx], xmm1"); // VMOVLPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x14, 0x0a], "vunpcklps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -177,6 +178,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0x0a], "vunpckhps xmm1, xmm0, xmmword [rdx]"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0x0a], "vunpckhps xmm1{k5}, xmm0, xmmword [rdx]"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0xca], "vmovlhps xmm1, xmm0, xmm2"); // VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x16, 0xca]); //
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0x0a], "vmovhps xmm1, xmm0, qword [rdx]"); // VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x0a], "vmovhps qword [rdx], xmm1"); // VMOVHPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0xca], "vmovaps ymm1{k5}{z}, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
@@ -217,9 +219,15 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2b, 0x0a], "vmovntps ymmword [rdx], ymm1"); // VMOVNTPS_MEMf32_YMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x2b, 0x0a], "vmovntps zmmword [rdx], zmm1"); // VMOVNTPS_MEMf32_ZMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x2b, 0x0a], "vmovntps xmmword [rdx], xmm1"); // VMOVNTPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x38, 0x2b, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xa8, 0x2b, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfc, 0x28, 0x2b, 0x0a]); // no W=1
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2e, 0xca], "vucomiss xmm1{sae}, xmm2"); // VUCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0xca], "vucomiss xmm1, xmm2"); // VUCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0x0a], "vucomiss xmm1, dword [rdx]"); // VUCOMISS_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x2e, 0x0a]); // no broadcast from memory
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x68, 0x2e, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x2e, 0x0a]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2f, 0xca], "vcomiss xmm1{sae}, xmm2"); // VCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0xca], "vcomiss xmm1, xmm2"); // VCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x0a], "vcomiss xmm1, dword [rdx]"); // VCOMISS_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -837,6 +845,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0xc2, 0xca, 0xcc], "vcmpps k1{sae}, zmm0, zmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}{sae}, zmm0, zmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc2, 0x0a, 0xcc], "vcmpps k1, ymm0, dword [rdx]{1to8}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0xb8, 0xc2, 0x0a, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0xca, 0xcc], "vcmpps k1, ymm0, ymm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, ymm0, ymm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -856,6 +865,7 @@ fn tests_None_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc6, 0x0a, 0xcc], "vshufps ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0xca, 0xcc]); // no broadcast from register source
     test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0xca, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -1016,10 +1026,16 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2b, 0x0a], "vmovntpd ymmword [rdx], ymm1"); // VMOVNTPD_MEMf64_YMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x2b, 0x0a], "vmovntpd zmmword [rdx], zmm1"); // VMOVNTPD_MEMf64_ZMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x2b, 0x0a], "vmovntpd xmmword [rdx], xmm1"); // VMOVNTPD_MEMf64_XMMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2b, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2b, 0x0a]); // no zero mask-merge
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x08, 0x2b, 0x0a]); // no W=-
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2e, 0xca], "vucomisd xmm1{sae}, xmm2"); // VUCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_invalid(&[0x62, 0xf1, 0xfd, 0x79, 0x2e, 0xca]); // mask reg must be 000
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0xca], "vucomisd xmm1, xmm2"); // VUCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0x0a], "vucomisd xmm1, qword [rdx]"); // VUCOMISD_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2e, 0x0a]); // no broadcast from memory
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x68, 0x2e, 0x0a]); // no L'L=11
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2e, 0x0a]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2f, 0xca], "vcomisd xmm1{sae}, xmm2"); // VCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0xca], "vcomisd xmm1, xmm2"); // VCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0x0a], "vcomisd xmm1, qword [rdx]"); // VCOMISD_XMMf64_MEMf64_AVX512, extension: AVX512EVEX
@@ -1752,8 +1768,10 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0x0a], "vpunpckhqdq xmm1, xmm0, xmmword [rdx]"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0xca], "vmovq xmm1, rdx"); // VMOVQ_XMMu64_GPR64u64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x6e, 0xca]); //no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0x0a], "vmovq xmm1, qword [rdx]"); // VMOVQ_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6e, 0xca], "vmovd xmm1, edx"); // VMOVD_XMMu32_GPR32u32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x6e, 0xca]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6e, 0x0a], "vmovd xmm1, dword [rdx]"); // VMOVD_XMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0xca], "vmovdqa64 ymm1{k5}{z}, ymm2"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0x0a], "vmovdqa64 ymm1{k5}{z}, ymmword [rdx]"); // VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX
@@ -2194,6 +2212,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0xca], "vmovq rdx, xmm1"); // VMOVQ_GPR64u64_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0x0a], "vmovq qword [rdx], xmm1"); // VMOVQ_MEMu64_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7e, 0xca], "vmovd edx, xmm1"); // VMOVD_GPR32u32_XMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x7e, 0xca]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7e, 0x0a], "vmovd dword [rdx], xmm1"); // VMOVD_MEMu32_XMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7f, 0xca], "vmovdqa64 ymm2{k5}{z}, ymm1"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0xca], "vmovdqa64 ymm2, ymm1"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
@@ -2229,6 +2248,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}{sae}, zmm0, zmm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, qword [rdx]{1to4}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0xc2, 0x0a, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0xca, 0xcc], "vcmppd k1, ymm0, ymm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, ymm0, ymm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, ymmword [rdx], 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
@@ -2720,6 +2740,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0x0a], "vpmulhw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{z}{sae}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0xe6, 0xca], "vcvttpd2dq ymm1{sae}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x78, 0xe6, 0xca]); // requires W=1
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{sae}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, qword [rdx]{1to4}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xe6, 0x0a], "vcvttpd2dq xmm1, qword [rdx]{1to4}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX
@@ -2751,6 +2772,7 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0x0a], "vmovntdq ymmword [rdx], ymm1"); // VMOVNTDQ_MEMu32_YMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe7, 0x0a], "vmovntdq zmmword [rdx], zmm1"); // VMOVNTDQ_MEMu32_ZMMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe7, 0x0a], "vmovntdq xmmword [rdx], xmm1"); // VMOVNTDQ_MEMu32_XMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0xca]); // no reg-reg encoding
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0xca], "vpsubsb ymm1{k5}{z}, ymm0, ymm2"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0x0a], "vpsubsb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0xca], "vpsubsb ymm1, ymm0, ymm2"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX
@@ -3068,6 +3090,8 @@ fn tests_66_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0x0a], "vpmaddwd xmm1{k5}, xmm0, xmmword [rdx]"); // VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0xca], "vpsadbw ymm1, ymm0, ymm2"); // VPSADBW_YMMu16_YMMu8_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0x0a], "vpsadbw ymm1, ymm0, ymmword [rdx]"); // VPSADBW_YMMu16_YMMu8_MEMu8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0xf6, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfd, 0xa8, 0xf6, 0x0a]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0xca], "vpsadbw zmm1, zmm0, zmm2"); // VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0x0a], "vpsadbw zmm1, zmm0, zmmword [rdx]"); // VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0xca], "vpsadbw xmm1, xmm0, xmm2"); // VPSADBW_XMMu16_XMMu8_XMMu8_AVX512, extension: AVX512EVEX
@@ -3285,6 +3309,8 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX
     test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2a, 0xca]); // mask reg must be 000
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0x0a], "vcvtsi2ss xmm1, xmm0, qword [rdx]"); // VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2a, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2a, 0xca], "vcvtsi2ss xmm1{rz-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x2a, 0xca], "vcvtsi2ss xmm1{rd-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX
@@ -3297,6 +3323,9 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0xca], "vcvttss2si rcx, xmm2"); // VCVTTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
     test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2c, 0xca]); // mask register must be 000
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0x0a], "vcvttss2si rcx, dword [rdx]"); // VCVTTSS2SI_GPR64i64_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2c, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x2c, 0x0a]); // no broadcast, regardless of W
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2c, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2c, 0xca], "vcvttss2si ecx{sae}, xmm2"); // VCVTTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); // VCVTTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2c, 0x0a], "vcvttss2si ecx, dword [rdx]"); // VCVTTSS2SI_GPR32i32_MEMf32_AVX512, extension: AVX512EVEX
@@ -3305,6 +3334,8 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0xca], "vcvtss2si rcx, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX
     test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2d, 0xca]); // mask register must be 000
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0x0a], "vcvtss2si rcx, dword [rdx]"); // VCVTSS2SI_GPR64i64_MEMf32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2d, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2d, 0xca], "vcvtss2si ecx{rz-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x2d, 0xca], "vcvtss2si ecx{rd-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2d, 0xca], "vcvtss2si ecx, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX
@@ -3603,6 +3634,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x7b, 0xca], "vcvtusi2ss xmm1{rd-sae}, xmm0, rdx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0xca], "vcvtusi2ss xmm1, xmm0, rdx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0x0a], "vcvtusi2ss xmm1, xmm0, qword [rdx]"); // VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x7b, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x7b, 0xca], "vcvtusi2ss xmm1{rz-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x7b, 0xca], "vcvtusi2ss xmm1{rd-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7b, 0xca], "vcvtusi2ss xmm1, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
@@ -3612,6 +3644,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x7b, 0xca], "vcvtusi2ss xmm1{ru-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x7b, 0xca], "vcvtusi2ss xmm1{rne-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0xca], "vmovq xmm1, xmm2"); // VMOVQ_XMMu64_XMMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xfe, 0x88, 0x7e, 0xca]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0x0a], "vmovq xmm1, qword [rdx]"); // VMOVQ_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x7f, 0xca], "vmovdqu64 ymm2{k5}{z}, ymm1"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0xca], "vmovdqu64 ymm2, ymm1"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
@@ -3647,6 +3680,7 @@ fn tests_f2_0f() {
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}{sae}, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0xca, 0xcc], "vcmpss k1, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0xc2, 0xca, 0xcc]); // do not allow L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0x0a, 0xcc], "vcmpss k1, xmm0, dword [rdx], 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpss k1{k5}, xmm0, dword [rdx], 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xfe, 0xfd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX
@@ -4063,6 +4097,7 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x7b, 0xca], "vcvtusi2sd xmm1{rd-sae}, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0xca], "vcvtusi2sd xmm1, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0x0a], "vcvtusi2sd xmm1, xmm0, qword [rdx]"); // VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x7b, 0x0a]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x7b, 0xca], "vcvtusi2sd xmm1, xmm0, edx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7b, 0x0a], "vcvtusi2sd xmm1, xmm0, dword [rdx]"); // VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x7b, 0xca], "vcvtusi2sd xmm1{ru-sae}, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX
@@ -4103,6 +4138,7 @@ fn tests_f3_0f() {
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0xca, 0xcc], "vcmpsd k1{k5}, xmm0, xmm2, 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0x0a, 0xcc], "vcmpsd k1, xmm0, qword [rdx], 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpsd k1{k5}, xmm0, qword [rdx], 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0xc2, 0x0a, 0xcc]); // no L'L=11
     test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rz-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0xe6, 0xca], "vcvtpd2dq ymm1{rz-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rz-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX
@@ -4848,6 +4884,8 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0x0a], "vpcmpeqq k1, xmm0, xmmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0x0a], "vpcmpeqq k1{k5}, xmm0, xmmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0x0a], "vmovntdqa ymm1, ymmword [rdx]"); // VMOVNTDQA_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0xca]); // no register source
+    test_invalid(&[0x62, 0xf2, 0x7d, 0xa8, 0x2a, 0x0a]); // no broadcast
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x0a], "vmovntdqa zmm1, zmmword [rdx]"); // VMOVNTDQA_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x0a], "vmovntdqa xmm1, xmmword [rdx]"); // VMOVNTDQA_XMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2b, 0x0a], "vpackusdw ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
@@ -7377,6 +7415,7 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0x0a], "vfmadd132ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
+    test_avx_full(&[0x62, 0xf2, 0x7d, 0x68, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); // no L'L==0 when not sae
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0xca], "vfmadd132ss xmm1{k5}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0x0a], "vfmadd132ss xmm1, xmm0, dword [rdx]"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0x0a], "vfmadd132ss xmm1{k5}, xmm0, dword [rdx]"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX
@@ -9194,6 +9233,8 @@ fn tests_66_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0x0a], "vgf2p8mulb xmm1{k5}, xmm0, xmmword [rdx]"); // VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0xca], "vaesenc ymm1, ymm0, ymm2"); // VAESENC_YMMu128_YMMu128_YMMu128_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0x0a], "vaesenc ymm1, ymm0, ymmword [rdx]"); // VAESENC_YMMu128_YMMu128_MEMu128_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0xfd, 0x38, 0xdc, 0x0a]); // no broadcast
+    test_invalid(&[0x62, 0xf2, 0xfd, 0xa8, 0xdc, 0x0a]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0xca], "vaesenc zmm1, zmm0, zmm2"); // VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0x0a], "vaesenc zmm1, zmm0, zmmword [rdx]"); // VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0xca], "vaesenc xmm1, xmm0, xmm2"); // VAESENC_XMMu128_XMMu128_XMMu128_AVX512, extension: AVX512EVEX
@@ -9467,6 +9508,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x28, 0xca], "vpmovm2w xmm1, k2"); // VPMOVM2W_XMMu16_MASKmskw_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x28, 0xca], "vpmovm2b zmm1, k2"); // VPMOVM2B_ZMMu8_MASKmskw_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x28, 0xca], "vpmovm2b xmm1, k2"); // VPMOVM2B_XMMu8_MASKmskw_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x28, 0xca]); //
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x29, 0xca], "vpmovw2m k1, ymm2"); // VPMOVW2M_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x29, 0xca], "vpmovb2m k1, ymm2"); // VPMOVB2M_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x29, 0xca], "vpmovw2m k1, zmm2"); // VPMOVW2M_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX
@@ -9574,6 +9616,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x38, 0xca], "vpmovm2d xmm1, k2"); // VPMOVM2D_XMMu32_MASKmskw_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x39, 0xca], "vpmovq2m k1, ymm2"); // VPMOVQ2M_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x39, 0xca], "vpmovd2m k1, ymm2"); // VPMOVD2M_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0xa8, 0x39, 0xca]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x39, 0xca], "vpmovq2m k1, zmm2"); // VPMOVQ2M_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x39, 0xca], "vpmovq2m k1, xmm2"); // VPMOVQ2M_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x39, 0xca], "vpmovd2m k1, zmm2"); // VPMOVD2M_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX
@@ -9581,6 +9624,7 @@ fn tests_f2_0f38() {
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x3a, 0xca], "vpbroadcastmw2d ymm1, k2"); // VPBROADCASTMW2D_YMMu32_MASKu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x3a, 0xca], "vpbroadcastmw2d zmm1, k2"); // VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x3a, 0xca], "vpbroadcastmw2d xmm1, k2"); // VPBROADCASTMW2D_XMMu32_MASKu32_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x3a, 0xca]); // no zero "mask merge", no masking at all
     test_avx_full(&[0x62, 0xf2, 0x7e, 0xbd, 0x52, 0x0a], "vdpbf16ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x52, 0x0a], "vdpbf16ps ymm1, ymm0, dword [rdx]{1to8}"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x52, 0x0a], "vdpbf16ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX
@@ -9712,6 +9756,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x00, 0x0a, 0xcc], "vpermq ymm1, qword [rdx]{1to4}, 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}, qword [rdx]{1to4}, 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}{z}, ymm2, 0xcc"); // VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0xca, 0xcc]); // no broadcast on reg-reg ops
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0xca, 0xcc], "vpermq ymm1, ymm2, 0xcc"); // VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}, ymm2, 0xcc"); // VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX
@@ -9802,6 +9847,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x04, 0x0a, 0xcc], "vpermilps ymm1, dword [rdx]{1to8}, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}, dword [rdx]{1to8}, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}{z}, ymm2, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0xca, 0xcc]); // no broadcast on reg sources
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0xca, 0xcc], "vpermilps ymm1, ymm2, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}, ymm2, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -9917,6 +9963,8 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, dword [rdx], 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x5d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0xca, 0xcc], "vrndscaless xmm1, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1, xmm0, dword [rdx], 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -9925,16 +9973,21 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xa8, 0x0b, 0xca, 0xcc]); // no zero-merge without mask reg
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, qword [rdx], 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1, xmm0, qword [rdx], 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0b, 0x0a, 0xcc]); // no broadcast on memory source
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x68, 0x0b, 0x0a, 0xcc]); // L'L==11 requires sae
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}, xmm0, qword [rdx], 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0xca, 0xcc], "vpalignr ymm1, ymm0, ymm2, 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}, ymm0, ymm2, 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x3d, 0x0f, 0xca, 0xcc]); // no broadcast
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0x0a, 0xcc], "vpalignr ymm1, ymm0, ymmword [rdx], 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0f, 0x0a, 0xcc]); // still no broadcast
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0xca, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0x0a, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
@@ -9949,14 +10002,22 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0x0a, 0xcc], "vpalignr xmm1, xmm0, xmmword [rdx], 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0x0a, 0xcc], "vpalignr xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0xca, 0xcc], "vpextrb edx, xmm1, 0xcc"); // VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x14, 0xca, 0xcc]); // no zero mask-merge, no masking!
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x14, 0xca, 0xcc]); // no broadcast
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0x0a, 0xcc], "vpextrb byte [rdx], xmm1, 0xcc"); // VPEXTRB_MEMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0xca, 0xcc], "vpextrw edx, xmm1, 0xcc"); // VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x15, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x15, 0xca, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0x0a, 0xcc], "vpextrw word [rdx], xmm1, 0xcc"); // VPEXTRW_MEMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0xca, 0xcc], "vpextrq rdx, xmm1, 0xcc"); // VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0x0a, 0xcc], "vpextrq qword [rdx], xmm1, 0xcc"); // VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x16, 0xca, 0xcc], "vpextrd edx, xmm1, 0xcc"); // VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x16, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x16, 0xca, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x16, 0x0a, 0xcc], "vpextrd dword [rdx], xmm1, 0xcc"); // VPEXTRD_MEMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0xca, 0xcc], "vextractps edx, xmm1, 0xcc"); // VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x17, 0xca, 0xcc]); // no broadcast
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x17, 0xca, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0x0a, 0xcc], "vextractps dword [rdx], xmm1, 0xcc"); // VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmmword [rdx], 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX
@@ -9992,6 +10053,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}, ymm1, 0xcc"); // VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [rdx], ymm1, 0xcc"); // VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [rdx]{k5}, ymm1, 0xcc"); // VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x19, 0x0a, 0xcc]); // no zero-merge with memmory dest
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2, zmm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}, zmm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
@@ -10024,6 +10086,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2{k5}, zmm1, 0xcc"); // VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [rdx], zmm1, 0xcc"); // VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xcd, 0x1b, 0x0a, 0xcc]); // no zero-merge into memory
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}{sae}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{sae}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{sae}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -10032,7 +10095,9 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}, ymm1, 0xcc"); // VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [rdx], ymm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [rdx]{k5}, ymm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x1d, 0x0a, 0xcc]); // no zero-merge into memory
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x1d, 0x0a, 0xcc]); // no L'L==11 for non-sae
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0x0a, 0xcc], "vcvtps2ph ymmword [rdx], zmm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX
@@ -10115,10 +10180,16 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0x0a, 0xcc], "vpcmpd k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0xca, 0xcc], "vpinsrb xmm1, xmm0, edx, 0xcc"); // VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x20, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x20, 0xca, 0xcc]); //
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0x0a, 0xcc], "vpinsrb xmm1, xmm0, byte [rdx], 0xcc"); // VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0xca, 0xcc], "vinsertps xmm1, xmm0, xmm2, 0xcc"); // VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x21, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x21, 0xca, 0xcc]); //
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0x0a, 0xcc], "vinsertps xmm1, xmm0, dword [rdx], 0xcc"); // VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0xca, 0xcc], "vpinsrq xmm1, xmm0, rdx, 0xcc"); // VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x22, 0xca, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x22, 0xca, 0xcc]); //
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0x0a, 0xcc], "vpinsrq xmm1, xmm0, qword [rdx], 0xcc"); // VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x22, 0xca, 0xcc], "vpinsrd xmm1, xmm0, edx, 0xcc"); // VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x22, 0x0a, 0xcc], "vpinsrd xmm1, xmm0, dword [rdx], 0xcc"); // VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX
@@ -10362,6 +10433,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0xca, 0xcc], "vpcmpub k1, ymm0, ymm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0xad, 0x3e, 0xca, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0x0a, 0xcc], "vpcmpub k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0xca, 0xcc], "vpcmpuw k1, zmm0, zmm2, 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX
@@ -10409,6 +10481,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1, ymm0, ymm2, 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymm2, 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1, ymm0, ymmword [rdx], 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0x7d, 0x38, 0x42, 0x0a, 0xcc]); // no broadcast
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX
@@ -10459,11 +10532,14 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1, zmm0, zmmword [rdx], 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0xca, 0xcc], "vpclmulqdq ymm1, ymm0, ymm2, 0xcc"); // VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x29, 0x44, 0xca, 0xcc]); // mask reg must be 000
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0x0a, 0xcc], "vpclmulqdq ymm1, ymm0, ymmword [rdx], 0xcc"); // VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0xca, 0xcc], "vpclmulqdq zmm1, zmm0, zmm2, 0xcc"); // VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0x0a, 0xcc], "vpclmulqdq zmm1, zmm0, zmmword [rdx], 0xcc"); // VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0xca, 0xcc], "vpclmulqdq xmm1, xmm0, xmm2, 0xcc"); // VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0x0a, 0xcc], "vpclmulqdq xmm1, xmm0, xmmword [rdx], 0xcc"); // VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x44, 0x0a, 0xcc]); //
+    test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x44, 0x0a, 0xcc]); //
     test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x50, 0xca, 0xcc], "vrangepd zmm1{sae}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX
@@ -10700,6 +10776,7 @@ fn tests_66_0f3a() {
     test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0x0a, 0xcc], "vreducess xmm1{k5}, xmm0, dword [rdx], 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [rdx]{1to4}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [rdx]{1to4}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX
+    test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x66, 0x0a, 0xcc]); // no zero mask-merge
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0xca, 0xcc], "vfpclasspd k1, ymm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, ymm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX
     test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0x0a, 0xcc], "vfpclasspd k1, ymmword [rdx], 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX