vblendv{ps,pd} precision

3 files changed, 19 insertions, 9 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 0132ca9..2db4bfa 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -24,7 +24,7 @@
 * fix incorrect operand order for VEX-encoded vmovupd opcode 0x11.
 * reject a few VEX-encoded instructions that are specific about allowed W-bits.
   vcvtph2ps, vbroadcastf128, vmaskmovps, vmaskmovpd, vpermd,
-  vpbroadcast{b,w,d,q}, vinserti128, vextracti128, among others
+  vpbroadcast{b,w,d,q}, vinserti128, vextracti128, vblendv*, among others.
 * vpbroadcastb and vpbroadcastw should respect the L bit to select xmm/ymm vector width, but
   always decoded as ymm.
 * vmaskmovqdu now reports a memory access size for the implied write to ds:[rdi/edi/di].
diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index 2a98166..89c36fb 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -2825,16 +2825,24 @@ fn read_vex_instruction<
                     } else {
                         return Err(DecodeError::InvalidOpcode);
                     }),
-                    0x4A => (Opcode::VBLENDVPS, if L {
-                        VEXOperandCode::G_V_E_ymm_ymm4
+                    0x4A => if instruction.prefixes.vex_unchecked().w() {
+                        return Err(DecodeError::InvalidOpcode);
                     } else {
-                        VEXOperandCode::G_V_E_xmm_xmm4
-                    }),
-                    0x4B => (Opcode::VBLENDVPD, if L {
-                        VEXOperandCode::G_V_E_ymm_ymm4
+                        (Opcode::VBLENDVPS, if L {
+                            VEXOperandCode::G_V_E_ymm_ymm4
+                        } else {
+                            VEXOperandCode::G_V_E_xmm_xmm4
+                        })
+                    },
+                    0x4B => if instruction.prefixes.vex_unchecked().w() {
+                        return Err(DecodeError::InvalidOpcode);
                     } else {
-                        VEXOperandCode::G_V_E_xmm_xmm4
-                    }),
+                        (Opcode::VBLENDVPD, if L {
+                            VEXOperandCode::G_V_E_ymm_ymm4
+                        } else {
+                            VEXOperandCode::G_V_E_xmm_xmm4
+                        })
+                    },
                     0x4C => if instruction.prefixes.vex_unchecked().w() {
                         return Err(DecodeError::InvalidOpcode);
                     } else {
diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs
index bb38f4c..cca08b4 100644
--- a/test/long_mode/mod.rs
+++ b/test/long_mode/mod.rs
@@ -2680,9 +2680,11 @@ fn test_vex() {
     test_instr(&[0xc4, 0xc3, 0x75, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], ymm6");
     test_instr(&[0xc4, 0xc3, 0x71, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps xmm7, xmm1, xmmword [r10 + rdx * 1 + 0x5], xmm6");
     test_instr(&[0xc4, 0xc3, 0x71, 0x4a, 0xdc, 0x61], "vblendvps xmm3, xmm1, xmm12, xmm6");
+    test_invalid(&[0xc4, 0xc3, 0xf1, 0x4a, 0xdc, 0x61]);
     test_instr(&[0xc4, 0xc3, 0x75, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], ymm6");
     test_instr(&[0xc4, 0xc3, 0x71, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd xmm7, xmm1, xmmword [r10 + rdx * 1 + 0x5], xmm6");
     test_instr(&[0xc4, 0xc3, 0x71, 0x4b, 0xdc, 0x61], "vblendvpd xmm3, xmm1, xmm12, xmm6");
+    test_invalid(&[0xc4, 0xc3, 0xf1, 0x4b, 0xdc, 0x61]);
     test_instr(&[0xc4, 0xc3, 0x71, 0x4c, 0x7c, 0x12, 0x05, 0x61], "vpblendvb xmm7, xmm1, xmmword [r10 + rdx * 1 + 0x5], xmm6");
 
     test_instr(&[0xc5, 0xc9, 0xf1, 0x0f], "vpsllw xmm1, xmm6, xmmword [rdi]");