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| author | iximeow <me@iximeow.net> | 2026-04-12 01:03:47 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-04-12 01:03:47 +0000 |
| commit | db39e9f141ca3746f16803afa35ac77b28ab4aff (patch) | |
| tree | 18a75d6e8df5f31e6f286e55229bf8c6c8044437 | |
| parent | 25eabe56e7f567565e6738273fecee4b87204a32 (diff) | |
note idt/gdt memory sizes being wrong
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -10,6 +10,8 @@ * push-immediate, pushf, popf, leave, and xlat now all report a correct memory access size, fixing the prior behavior of reporting to memory access size at all +* table load/store instructions (lgdt, lidt, lldt, sgdt, sidt, sldt) have correct (mode-dependent) + memory access sizes, rather than incorrectly varying on operand-size overrides. * 64-bit mode: mov seg-to-reg uses 32-bit GPRs for the destination rather than 16-bit. * this is more accurate to the semantic of the instruction, which is why other disassemblers report it this way; for register destinations specifically the segment selector is |