aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authoriximeow <me@iximeow.net>2020-08-03 01:51:39 -0700
committeriximeow <me@iximeow.net>2020-08-09 01:38:57 -0700
commit97f1c7e15a35df264dae91d76660db4762bd5d25 (patch)
treec5774b6525a670fe4d58ee84446c86a7c373fc87
parent37c43412cbdd7c5da1da2ee17c241d44e9720ae2 (diff)
vpermq (avx2)
-rw-r--r--src/long_mode/vex.rs13
-rw-r--r--test/long_mode/mod.rs1
2 files changed, 13 insertions, 1 deletions
diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index cdca801..8325e3f 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -772,8 +772,19 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
instruction.vex_reg.bank = bank;
Ok(())
}
+ VEXOperandCode::G_E_ymm_imm8 => {
+ let modrm = read_modrm(bytes, length)?;
+ instruction.modrm_rrr =
+ RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
+ let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+ instruction.operands[0] = OperandSpec::RegRRR;
+ instruction.operands[1] = mem_oper;
+ instruction.imm = read_imm_unsigned(bytes, 1, length)?;
+ instruction.operands[2] = OperandSpec::ImmU8;
+ instruction.operand_count = 3;
+ Ok(())
+ }
- VEXOperandCode::G_E_ymm_imm8 |
VEXOperandCode::G_V_E_xmm_xmm4 |
VEXOperandCode::G_V_E_ymm_ymm4 |
VEXOperandCode::G_V_ymm_E_xmm |
diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs
index 3d9a22c..67b2b66 100644
--- a/test/long_mode/mod.rs
+++ b/test/long_mode/mod.rs
@@ -1386,6 +1386,7 @@ fn test_vex() {
test_instr_invalid(&[0xc4, 0xe3, 0xf9, 0x14, 0x00, 0xd0]);
test_instr_invalid(&[0xc4, 0xe3, 0xf9, 0x14, 0x00, 0x0a]);
test_instr(&[0xc5, 0xed, 0x71, 0xd0, 0x04], "vpsrlw ymm2, ymm0, 0x4");
+ test_instr(&[0xc4, 0xe3, 0xfd, 0x00, 0xc1, 0xa8], "vpermq ymm0, ymm1, 0xa8");
}
#[test]