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authoriximeow <me@iximeow.net>2020-08-09 20:49:12 -0700
committeriximeow <me@iximeow.net>2020-08-09 20:49:12 -0700
commit6248d3c5f7dd196acdfce5c0da1608fed81b43cd (patch)
treeb38ed1edaf50708b5e9774a29a9ae09ec1b50481 /CHANGELOG
parent8f857a2fcbdfc7315cd09c0a4ac372b3ec92b538 (diff)
inaugural 0.1.0 release!0.1.0
add doc comments for public items, record changelog, and lets ship this!!
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* support x86_32 `pusha`/`popa`
* support x86_32 BCD instructions
- for `aam`/`aad`, the undocumented `amx` and `adx` forms are used in all cases, including when the base is 10
+* begin some proper documentation for public items
+
+/!\ BREAKING CHANGES /!\
+* `RegisterBank` is no longer public. `RegisterClass` should be a suitable
+ replacement, accessible via `reg.class()`, with the register class name
+ available by `reg.class().name`, and size available by `reg.class().width()`.
+ `reg.width()` still works, and just forwards to `reg.class().width()`.
+* the field `opcode` of `Instruction` is no longer public. it can now be accessed by `inst.opcode()`.
## 0.0.15