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authoriximeow <me@iximeow.net>2019-10-21 00:52:48 -0700
committeriximeow <me@iximeow.net>2020-01-12 16:10:13 -0800
commit37e8c767c1d84c47adaa763433c87766cece4050 (patch)
tree9be04ea24936557a4be3b186ed36d58922feb25c /src/lib.rs
parentbeccdec482bfc03d6bbbf413d2a7604183eb8f86 (diff)
more squeezing!!
Diffstat (limited to 'src/lib.rs')
-rw-r--r--src/lib.rs16
1 files changed, 9 insertions, 7 deletions
diff --git a/src/lib.rs b/src/lib.rs
index 51eb232..c59711a 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -2536,13 +2536,15 @@ pub fn read_operands<T: Iterator<Item=u8>>(mut bytes_iter: T, instruction: &mut
mem_oper = read_E(&mut bytes_iter, instruction, modrm, opwidth)?;
}
- if operand_code == OperandCode::Gv_Ev || operand_code == OperandCode::Gb_Eb {
- instruction.operands[1] = mem_oper;
- instruction.operands[0] = OperandSpec::RegRRR;
- instruction.operand_count = 2;
- } else if operand_code == OperandCode::Ev_Gv || operand_code == OperandCode::Eb_Gb {
- instruction.operands[0] = mem_oper;
- instruction.operands[1] = OperandSpec::RegRRR;
+ let numeric_code = operand_code as u8;
+ if numeric_code >= 0x80 && numeric_code < 0x84 {
+ let (mmm, rrr) = if numeric_code & 0x02 == 2 {
+ (1, 0)
+ } else {
+ (0, 1)
+ };
+ instruction.operands[mmm] = mem_oper;
+ instruction.operands[rrr] = OperandSpec::RegRRR;
instruction.operand_count = 2;
} else if operand_code == OperandCode::Jbs {
// TODO: arch width (8 in 64, 4 in 32, 2 in 16)