diff options
author | iximeow <me@iximeow.net> | 2021-07-01 23:54:06 -0700 |
---|---|---|
committer | iximeow <me@iximeow.net> | 2021-07-01 23:54:06 -0700 |
commit | a781322552d9fb52b7b5e51641f49f12678f682f (patch) | |
tree | b7ea7042d707dca8ffc322ddac4ebd5b8c475027 /src/long_mode/display.rs | |
parent | 889ce5c55af062d12cdd109bac22cc05565f68a6 (diff) |
reallocate OperandCode, convert disparate registers to array
also remove redundant assignments of operand_count and some OperandSpec,
bulk-assign all registers and operands on entry to `read_instr`. this
all, taken together, shaves off about 7 cycles per decode.
Diffstat (limited to 'src/long_mode/display.rs')
-rw-r--r-- | src/long_mode/display.rs | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs index 107eb94..e60645b 100644 --- a/src/long_mode/display.rs +++ b/src/long_mode/display.rs @@ -3400,7 +3400,13 @@ fn contextualize_intel<T: fmt::Write, Y: YaxColors>(instr: &Instruction, colors: } } } else { - Operand::from_spec(instr, instr.operands[i as usize - 1]).width() / instr.mem_size + // this should never be `None` - that would imply two + // memory operands for a broadcasted operation. + if let Some(width) = Operand::from_spec(instr, instr.operands[i as usize - 1]).width() { + width / instr.mem_size + } else { + 0 + } }; write!(out, "{{1to{}}}", scale)?; } |