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| author | Bruce Mitchener <bruce.mitchener@gmail.com> | 2022-09-17 17:31:08 +0700 |
|---|---|---|
| committer | iximeow <git@iximeow.net> | 2022-09-23 00:29:30 -0700 |
| commit | a36f07578272821cfad2c940b00a5600fd03c793 (patch) | |
| tree | 0f826a966220633d9ad0a2d9112bbb66c81880bb /src/long_mode/mod.rs | |
| parent | 093781f2652416c28927c76b9ada05ba6450b330 (diff) | |
Fix some typos.
Diffstat (limited to 'src/long_mode/mod.rs')
| -rw-r--r-- | src/long_mode/mod.rs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 2f3e510..b4f296e 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -399,7 +399,7 @@ pub enum Operand { /// instruction uses this mode. as an example, `[0x1133]` DisplacementU32(u32), /// a memory access to a literal qword address. it's relatively rare that a well-formed x86 - /// instruction uses this mode, but plausibe. for example, `gs:[0x14]`. segment overrides, + /// instruction uses this mode, but plausible. for example, `gs:[0x14]`. segment overrides, /// however, are maintained on the instruction itself. DisplacementU64(u64), /// a simple dereference of the address held in some register. for example: `[rsi]`. @@ -516,7 +516,7 @@ impl OperandSpec { /// /// the behavior for non-`avx512` instructions is equivalent to `merge`. `zero` is only useful in /// conjunction with a mask register, where bits specified in the mask register correspond to -/// unmodified items in the instruction's desination. +/// unmodified items in the instruction's destination. #[derive(Debug, Copy, Clone, PartialEq, Eq)] pub enum MergeMode { Merge, @@ -2660,7 +2660,7 @@ enum OperandSpec { RegRRR_maskmerge_sae_noround, // the register in modrm_mmm (eg modrm mod bits were 11) RegMMM, - // same as `RegRRR`: the register is modrm's `mmm` bits, and may be masekd. + // same as `RegRRR`: the register is modrm's `mmm` bits, and may be masked. RegMMM_maskmerge, RegMMM_maskmerge_sae_noround, // the register selected by vex-vvvv bits @@ -3259,7 +3259,7 @@ impl InstDecoder { } /// enable all `avx512` features on this `InstDecoder`. no real CPU, at time of writing, - /// actually has such a feature comination, but this is a useful overestimate for `avx512` + /// actually has such a feature combination, but this is a useful overestimate for `avx512` /// generally. pub fn with_avx512(mut self) -> Self { let avx512_mask = |