diff options
| author | iximeow <me@iximeow.net> | 2020-08-09 00:32:49 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2020-08-09 01:39:01 -0700 |
| commit | 2bf6df7ff4101b4e7cf14807b5e9def85d92e1cd (patch) | |
| tree | e2555f6a9468582422baafe95aea243a2a05d7a1 /src/long_mode/mod.rs | |
| parent | a3f848e3426175d9ac782c19de4855de260d76a9 (diff) | |
display opt, aykm
the arms of the match in regspec_label referenced tables that were not
const. consequently, they would be rebuilt when reached, every time the
match is incanted. this holds through even when regspec_label is
inlined.
each arm could be a const array for a small and easy change, but to
avoid the indirect dispatch on spec.bank i've reorganized register names
into a single const array and selected values for `RegisterBank` such
that indices into that array can be formed.
for my next trick, i may make `REG_NAMES` a `*const u8`, with indices
picking offsets into the table - 8-byte offsets might do? this should
compact down size a little more by removing a pointer and size qword
for each string.
Diffstat (limited to 'src/long_mode/mod.rs')
| -rw-r--r-- | src/long_mode/mod.rs | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 9d3b05a..3b3bddb 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -508,21 +508,21 @@ fn operand_size() { #[cfg(feature="use-serde")] #[derive(Copy, Clone, Debug, Ord, PartialOrd, Eq, PartialEq, Hash, Serialize, Deserialize)] pub enum RegisterBank { - Q, D, W, B, rB, // Quadword, Dword, Word, Byte - CR, DR, S, EIP, RIP, EFlags, RFlags, // Control reg, Debug reg, Selector, ... - X, Y, Z, // XMM, YMM, ZMM - ST, MM, // ST, MM regs (x87, mmx) - K, // AVX512 mask registers + Q = 0, D = 2, W = 4, B = 6, rB = 8, // Quadword, Dword, Word, Byte + CR = 10, DR = 12, S = 14, EIP = 30, RIP = 31, EFlags = 32, RFlags = 33, // Control reg, Debug reg, Selector, ... + X = 15, Y = 19, Z = 23, // XMM, YMM, ZMM + ST = 27, MM = 28, // ST, MM regs (x87, mmx) + K = 29, // AVX512 mask registers } #[allow(non_camel_case_types)] #[cfg(not(feature="use-serde"))] #[derive(Copy, Clone, Debug, Ord, PartialOrd, Eq, PartialEq, Hash)] pub enum RegisterBank { - Q, D, W, B, rB, // Quadword, Dword, Word, Byte - CR, DR, S, EIP, RIP, EFlags, RFlags, // Control reg, Debug reg, Selector, ... - X, Y, Z, // XMM, YMM, ZMM - ST, MM, // ST, MM regs (x87, mmx) - K, // AVX512 mask registers + Q = 0, D = 2, W = 4, B = 6, rB = 8, // Quadword, Dword, Word, Byte + CR = 10, DR = 12, S = 14, EIP = 30, RIP = 31, EFlags = 32, RFlags = 33, // Control reg, Debug reg, Selector, ... + X = 15, Y = 19, Z = 23, // XMM, YMM, ZMM + ST = 27, MM = 28, // ST, MM regs (x87, mmx) + K = 29, // AVX512 mask registers } #[derive(Copy, Clone, Debug, Eq, PartialEq, Hash)] |