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author | iximeow <me@iximeow.net> | 2021-07-03 13:39:46 -0700 |
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committer | iximeow <me@iximeow.net> | 2021-07-03 13:43:39 -0700 |
commit | 7796f7e088c5aa878cfb61b5a885b64daf390808 (patch) | |
tree | e070d42e01c88aba9efea534749160f191b9483b /src/long_mode/mod.rs | |
parent | 2e34ef39d75caeb10c499712bc28ac9de8abf984 (diff) |
clean up x86_32 and make interfaces match x86_64
Diffstat (limited to 'src/long_mode/mod.rs')
-rw-r--r-- | src/long_mode/mod.rs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 0cae4f0..04ad91b 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -9154,14 +9154,14 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y } } OperandCode::ModRM_0x0f01 => { - if instruction.prefixes.rep() || instruction.prefixes.repnz() { - return Err(DecodeError::InvalidOperand); - } - let opwidth = imm_width_from_prefixes_64(SizeCode::vq, instruction.prefixes); let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; if r == 0 { + if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { + return Err(DecodeError::InvalidOperand); + } + let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { |