diff options
author | iximeow <me@iximeow.net> | 2020-08-09 19:25:07 -0700 |
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committer | iximeow <me@iximeow.net> | 2020-08-09 19:25:07 -0700 |
commit | 57ff56d8b5c3a3fa4f1d7f4881afbe2ce8e47cfd (patch) | |
tree | 81ed40ad1545fb88933245a7b2f78f53242c4ac8 /src/long_mode/mod.rs | |
parent | c06dd09585d192199f8f3068c69aecfae5d407f6 (diff) |
support salc, get segment register numbers right
Diffstat (limited to 'src/long_mode/mod.rs')
-rw-r--r-- | src/long_mode/mod.rs | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 3fcf4ab..4d663d3 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -158,12 +158,12 @@ impl RegSpec { #[inline] pub fn fs() -> RegSpec { - RegSpec { bank: RegisterBank::S, num: 3 } + RegSpec { bank: RegisterBank::S, num: 4 } } #[inline] pub fn gs() -> RegSpec { - RegSpec { bank: RegisterBank::S, num: 4 } + RegSpec { bank: RegisterBank::S, num: 5 } } #[inline] @@ -1450,6 +1450,7 @@ pub enum Opcode { WRGSBASE, CRC32, + SALC, XLAT, F2XM1, @@ -5200,7 +5201,7 @@ const OPCODES: [OpcodeRecord; 256] = [ OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd3_Ev_CL), OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), + OpcodeRecord(Interpretation::Instruction(Opcode::SALC), OperandCode::Nothing), // XLAT OpcodeRecord(Interpretation::Instruction(Opcode::XLAT), OperandCode::Nothing), // x86 d8 |