diff options
| author | iximeow <me@iximeow.net> | 2023-02-12 11:43:39 -0800 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2023-07-04 19:01:38 -0700 |
| commit | 940a46d0ba4b9d833e3670f699ba48cf4782ee8b (patch) | |
| tree | db27d696aae1af1288ab0b9bd8471c69c4737589 /src/long_mode/mod.rs | |
| parent | 64cc541f8aa11823b339d5900b64109d5ad738ab (diff) | |
fix xbegin/xend (broken in DecodeCtx::rrr)
Diffstat (limited to 'src/long_mode/mod.rs')
| -rw-r--r-- | src/long_mode/mod.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 30440c6..ad7a782 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -7200,7 +7200,7 @@ fn read_operands< }, OperandCase::MovI8 => { if self.rrr != 0 { - if mem_oper == OperandSpec::RegMMM && self.rrr == 0 { + if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XABORT; instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( @@ -7237,7 +7237,7 @@ fn read_operands< OperandCase::MovIv => { let opwidth = instruction.regs[0].bank as u8; if self.rrr != 0 { - if mem_oper == OperandSpec::RegMMM && self.rrr == 0 { + if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XBEGIN; instruction.imm = if opwidth == 2 { let imm = read_imm_signed(words, 2)? as i16 as i64 as u64; |