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authoriximeow <me@iximeow.net>2021-07-02 19:45:34 -0700
committeriximeow <me@iximeow.net>2021-07-02 19:45:34 -0700
commit7394c9dc4727d42b3ccbdf38f114ae0b5d28069d (patch)
tree21da3f7098b8fbdd3e58ec4b9359d1e002d07703 /src/long_mode/mod.rs
parent0b04fd05a955033dc781caaec6eb2b32f85c1b3f (diff)
intel keylocker instructions that access memory have memory access sizes
Diffstat (limited to 'src/long_mode/mod.rs')
-rw-r--r--src/long_mode/mod.rs8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 22ffe58..e8947ea 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -8610,6 +8610,7 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
if modrm >= 0b11_000_000 {
return Err(DecodeError::InvalidOperand);
}
+ instruction.mem_size = 48;
instruction.opcode = Opcode::AESENCWIDE128KL;
instruction.operands[0] = read_M(words, instruction, modrm)?;
return Ok(());
@@ -8618,6 +8619,7 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
if modrm >= 0b11_000_000 {
return Err(DecodeError::InvalidOperand);
}
+ instruction.mem_size = 48;
instruction.opcode = Opcode::AESDECWIDE128KL;
instruction.operands[0] = read_M(words, instruction, modrm)?;
return Ok(());
@@ -8626,6 +8628,7 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
if modrm >= 0b11_000_000 {
return Err(DecodeError::InvalidOperand);
}
+ instruction.mem_size = 64;
instruction.opcode = Opcode::AESENCWIDE256KL;
instruction.operands[0] = read_M(words, instruction, modrm)?;
return Ok(());
@@ -8634,6 +8637,7 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
if modrm >= 0b11_000_000 {
return Err(DecodeError::InvalidOperand);
}
+ instruction.mem_size = 64;
instruction.opcode = Opcode::AESDECWIDE256KL;
instruction.operands[0] = read_M(words, instruction, modrm)?;
return Ok(());
@@ -8648,6 +8652,7 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
if let OperandSpec::RegMMM = instruction.operands[1] {
instruction.opcode = Opcode::LOADIWKEY;
} else {
+ instruction.mem_size = 48;
instruction.opcode = Opcode::AESENC128KL;
}
}
@@ -8656,6 +8661,7 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
if let OperandSpec::RegMMM = instruction.operands[1] {
return Err(DecodeError::InvalidOperand);
} else {
+ instruction.mem_size = 48;
instruction.opcode = Opcode::AESDEC128KL;
}
}
@@ -8664,6 +8670,7 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
if let OperandSpec::RegMMM = instruction.operands[1] {
return Err(DecodeError::InvalidOperand);
} else {
+ instruction.mem_size = 64;
instruction.opcode = Opcode::AESENC256KL;
}
}
@@ -8672,6 +8679,7 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
if let OperandSpec::RegMMM = instruction.operands[1] {
return Err(DecodeError::InvalidOperand);
} else {
+ instruction.mem_size = 64;
instruction.opcode = Opcode::AESDEC256KL;
}
}