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authoriximeow <me@iximeow.net>2023-12-15 17:26:59 -0800
committeriximeow <me@iximeow.net>2023-12-15 17:26:59 -0800
commit003183a4ce31cfb718f4e4083d32c845352c2321 (patch)
treee6931eb0d6baa7eaa99a2386e8d13a6037fd421f /src/long_mode/mod.rs
parent792eb993a87fab799b3a6659c7750f2221608cbf (diff)
more RegSpec constructor validation, fix bug in x86_64 1b reg specs
* the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be constructed in two ways that produce "identical" `RegSpec` that are.. not. e.g. `RegSpec::al() != Regspec::rb(0)` even though `RegSpec::al().name() == RegSpec::rb(0).name()`. this corrects the `rb` constructor at least, but instructions like `4830c0` and `30c0` still produce incompatible versions of `al`. * also fix register numbering used explicit qword-sized RegSpec constructors, r12 and r13 used to produce r8 and r9
Diffstat (limited to 'src/long_mode/mod.rs')
-rw-r--r--src/long_mode/mod.rs10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 5132973..7f9719c 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -236,9 +236,15 @@ impl RegSpec {
panic!("invalid x86 rex-byte reg {}", num);
}
+ let bank = if num < 4 {
+ RegisterBank::B
+ } else {
+ RegisterBank::rB
+ };
+
RegSpec {
num,
- bank: RegisterBank::rB
+ bank,
}
}
@@ -283,7 +289,7 @@ impl RegSpec {
rax => 0, rcx => 1, rdx => 2, rbx => 3,
rsp => 4, rbp => 5, rsi => 6, rdi => 7,
r8 => 8, r9 => 9, r10 => 10, r11 => 11,
- r12 => 8, r13 => 9, r14 => 14, r15 => 15
+ r12 => 12, r13 => 13, r14 => 14, r15 => 15
);
register!(D,