diff options
| author | iximeow <me@iximeow.net> | 2026-04-17 02:22:24 +0000 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2026-04-17 02:22:24 +0000 |
| commit | 5e9c3238e2d7f4565c510f396c57864901d76827 (patch) | |
| tree | 874e3444a3a669c7e1d86d9de3f7d4ae7d5f6964 /src/long_mode/mod.rs | |
| parent | 6e41e945552dde69ab15bfa63e4d2bb20b5efc34 (diff) | |
more precise about 0f0d prefetch/nop
Diffstat (limited to 'src/long_mode/mod.rs')
| -rw-r--r-- | src/long_mode/mod.rs | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 06e5b21..6433464 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -7239,12 +7239,14 @@ fn read_operands< instruction.opcode = Opcode::NOP; } } - instruction.operands[0] = mem_oper; - if instruction.operands[0] != OperandSpec::RegMMM { - instruction.mem_size = 64; - } else { - instruction.regs[1].bank = bank; + if mem_oper == OperandSpec::RegMMM { + // *found* this from running `0f0dc0` under KVM on a Zen 5 system. this is + // consistent with the register number being used to pick kinds of prefetch. + return Err(DecodeError::InvalidOperand); } + + instruction.operands[0] = mem_oper; + instruction.mem_size = 64; instruction.operand_count = 1; } OperandCase::ModRM_0x0f0f => { |
