diff options
author | iximeow <me@iximeow.net> | 2021-03-21 03:19:51 -0700 |
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committer | iximeow <me@iximeow.net> | 2021-03-21 03:19:51 -0700 |
commit | 22baa577c5ba34bc4e89b7019f2666ff7cee4b07 (patch) | |
tree | 6f24d944f447f8a28d9f1d2f6a1f2ee2f776a604 /src/long_mode/mod.rs | |
parent | d7b07d3eb6e6dc614fbc13cb66b951cb93daec44 (diff) |
add tsxldtrk
does intel know no bounds
Diffstat (limited to 'src/long_mode/mod.rs')
-rw-r--r-- | src/long_mode/mod.rs | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 6a85542..2c4ac92 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -1966,6 +1966,10 @@ pub enum Opcode { CLUI, STUI, SENDUIPI, + + // TSXLDTRK + XSUSLDTRK, + XRESLDTRK, } #[derive(Debug)] @@ -8326,6 +8330,12 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter let m = modrm & 7; match m { 0b000 => { + if instruction.prefixes.repnz() { + instruction.opcode = Opcode::XSUSLDTRK; + instruction.operands[0] = OperandSpec::Nothing; + instruction.operand_count = 0; + return Ok(()); + } if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } @@ -8333,6 +8343,15 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } + 0b001 => { + if instruction.prefixes.repnz() { + instruction.opcode = Opcode::XRESLDTRK; + instruction.operands[0] = OperandSpec::Nothing; + instruction.operand_count = 0; + return Ok(()); + } + return Err(DecodeError::InvalidOpcode); + } 0b010 => { if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); |