diff options
| author | iximeow <me@iximeow.net> | 2021-03-21 01:02:00 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-03-21 01:21:55 -0700 |
| commit | a493b4d267c4fb6a042cf071301c8885196b4a91 (patch) | |
| tree | 9be24cf43e2fef9f48d6f88e0b7716eb5f66ccca /src/long_mode/vex.rs | |
| parent | 0c8dccaf591748e6acb9b437d69ba028e59a73cf (diff) | |
rewrite 0f-based instruction handling
this is... a more significant rewrite than i expected yaxpeax-x86 to
ever need. it turns out that capstone is extremely permissive about
duplicative 66/f2/f3 prefixes to the point that the implemented prefex
handling was unsalvageable.
while this replaces the *0f* opcode tables, i haven't profiled these
changes. it's possible this is a net improvement for single-byte
opcodes, it could be a net loss. code size may be severely impacted.
there is still work to do.
but this in total gets very close to iced/xed/zydis parity, far more
than before.
also adds several small extensions, gfni, 3dnow, enqcmd, invpcid, some
of cet, and a few missing avx instructions.
Diffstat (limited to 'src/long_mode/vex.rs')
| -rw-r--r-- | src/long_mode/vex.rs | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs index bbfd508..71a5724 100644 --- a/src/long_mode/vex.rs +++ b/src/long_mode/vex.rs @@ -942,6 +942,16 @@ fn read_vex_instruction<T: Iterator<Item=u8>>(opcode_map: VEXOpcodeMap, bytes: & } else { VEXOperandCode::G_E_xmm }), + 0x54 => (Opcode::VANDPS, if L { + VEXOperandCode::G_V_E_ymm + } else { + VEXOperandCode::G_V_E_xmm + }), + 0x55 => (Opcode::VANDNPS, if L { + VEXOperandCode::G_V_E_ymm + } else { + VEXOperandCode::G_V_E_xmm + }), 0x57 => (Opcode::VXORPS, if L { VEXOperandCode::G_V_E_ymm } else { @@ -1079,6 +1089,16 @@ fn read_vex_instruction<T: Iterator<Item=u8>>(opcode_map: VEXOpcodeMap, bytes: & } else { VEXOperandCode::G_E_xmm }), + 0x54 => (Opcode::VANDPD, if L { + VEXOperandCode::G_V_E_ymm + } else { + VEXOperandCode::G_V_E_xmm + }), + 0x55 => (Opcode::VANDNPD, if L { + VEXOperandCode::G_V_E_ymm + } else { + VEXOperandCode::G_V_E_xmm + }), 0x57 => (Opcode::VXORPD, if L { VEXOperandCode::G_V_E_ymm } else { |