support four-reg operand forms, new tests

1 files changed, 28 insertions, 0 deletions

diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index 8563fc7..7c4e27d 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -798,6 +798,34 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
             instruction.operand_count = 3;
             Ok(())
         }
+        VEXOperandCode::G_V_E_ymm_ymm4 => {
+            let modrm = read_modrm(bytes, length)?;
+            instruction.modrm_rrr =
+                RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), RegisterBank::Y);
+            instruction.vex_reg.bank = RegisterBank::Y;
+            let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
+            instruction.operands[0] = OperandSpec::RegRRR;
+            instruction.operands[1] = OperandSpec::RegVex;
+            instruction.operands[2] = mem_oper;
+            instruction.imm = read_imm_unsigned(bytes, 1, length)? >> 4;
+            instruction.operands[3] = OperandSpec::Reg4;
+            instruction.operand_count = 4;
+            Ok(())
+        }
+        VEXOperandCode::G_V_E_xmm_xmm4 => {
+            let modrm = read_modrm(bytes, length)?;
+            instruction.modrm_rrr =
+                RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), RegisterBank::X);
+            instruction.vex_reg.bank = RegisterBank::X;
+            let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
+            instruction.operands[0] = OperandSpec::RegRRR;
+            instruction.operands[1] = OperandSpec::RegVex;
+            instruction.operands[2] = mem_oper;
+            instruction.imm = read_imm_unsigned(bytes, 1, length)? >> 4;
+            instruction.operands[3] = OperandSpec::Reg4;
+            instruction.operand_count = 4;
+            Ok(())
+        }
 
         VEXOperandCode::G_V_E_xmm_xmm4 |
         VEXOperandCode::G_V_E_ymm_ymm4 |