diff options
| author | iximeow <me@iximeow.net> | 2021-07-04 12:20:13 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-07-04 12:36:03 -0700 |
| commit | 48559b18574b44e2de879a5c641ab602ec22f0d8 (patch) | |
| tree | 0195cd249c1ce2429b12a14d063447fe96e3283e /src/long_mode | |
| parent | 404cb6e81988ed84a75c89d67bf324409e22a390 (diff) | |
fix several incorrect tests and docs in 64- and 32-bit modes
Diffstat (limited to 'src/long_mode')
| -rw-r--r-- | src/long_mode/mod.rs | 2 | ||||
| -rw-r--r-- | src/long_mode/vex.rs | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 600a81a..79f3fee 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -7673,7 +7673,7 @@ fn read_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpe if opcode == Opcode::CALL || opcode == Opcode::JMP || opcode == Opcode::PUSH || opcode == Opcode::POP { instruction.mem_size = 8; } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { - instruction.mem_size = 9; + instruction.mem_size = 10; } } instruction.opcode = opcode; diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs index 67c4965..5695b17 100644 --- a/src/long_mode/vex.rs +++ b/src/long_mode/vex.rs @@ -411,7 +411,7 @@ fn read_vex_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y instruction.opcode = if modrm & 0xc0 == 0xc0 { Opcode::VMOVHLPS } else { - instruction.mem_size = 4; + instruction.mem_size = 8; Opcode::VMOVLPS }; instruction.regs[0] = @@ -1925,7 +1925,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a } else { VEXOperandCode::G_V_E_xmm }), - 0xDA => (Opcode::VPMINSW, if L { + 0xDA => (Opcode::VPMINUB, if L { VEXOperandCode::G_V_E_ymm } else { VEXOperandCode::G_V_E_xmm @@ -3201,12 +3201,12 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a VEXOperandCode::G_E_xmm_imm8 }), 0x0A => (Opcode::VROUNDSS, if L { - VEXOperandCode::G_V_E_ymm_imm8 + VEXOperandCode::G_V_E_xmm_imm8 } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x0B => (Opcode::VROUNDSD, if L { - VEXOperandCode::G_V_E_ymm_imm8 + VEXOperandCode::G_V_E_xmm_imm8 } else { VEXOperandCode::G_V_E_xmm_imm8 }), @@ -3269,7 +3269,7 @@ fn read_vex_instruction<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a return Err(DecodeError::InvalidOpcode); } else { (Opcode::VINSERTF128, if L { - VEXOperandCode::G_V_E_ymm_imm8 + VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 } else { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOpcode); |