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authoriximeow <me@iximeow.net>2021-03-21 11:40:56 -0700
committeriximeow <me@iximeow.net>2021-03-21 11:41:18 -0700
commit12251de92baadedbecca2048740959b0f965ffc5 (patch)
treedc1aef6565d3241f8a6682cfb6ad7eb915bd083d /src/long_mode
parent22baa577c5ba34bc4e89b7019f2666ff7cee4b07 (diff)
fix potential successful decodes with Opcode::Invalid
vmov* are.. somehow messed up too
Diffstat (limited to 'src/long_mode')
-rw-r--r--src/long_mode/mod.rs22
-rw-r--r--src/long_mode/vex.rs4
2 files changed, 17 insertions, 9 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 2c4ac92..1e3f568 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -6516,12 +6516,6 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T,
// match operand_code {
match operand_code.special_case_handler_index() {
0 => {
- // turns out xed cand capstone both permit nonzero rrr bits here.
- // if (modrm & 0b00111000) != 0 {
- // instruction.opcode = Opcode::Invalid;
- // return Err(DecodeError::InvalidOperand);
- //}
-
instruction.operands[0] = mem_oper;
instruction.operand_count = 1;
},
@@ -8349,8 +8343,12 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
instruction.operands[0] = OperandSpec::Nothing;
instruction.operand_count = 0;
return Ok(());
+ } else {
+ instruction.opcode = Opcode::Invalid;
+ instruction.operands[0] = OperandSpec::Nothing;
+ instruction.operand_count = 0;
+ return Err(DecodeError::InvalidOpcode);
}
- return Err(DecodeError::InvalidOpcode);
}
0b010 => {
if !instruction.prefixes.rep() || instruction.prefixes.repnz() {
@@ -8365,6 +8363,11 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
instruction.opcode = Opcode::UIRET;
instruction.operands[0] = OperandSpec::Nothing;
instruction.operand_count = 0;
+ } else {
+ instruction.opcode = Opcode::Invalid;
+ instruction.operands[0] = OperandSpec::Nothing;
+ instruction.operand_count = 0;
+ return Err(DecodeError::InvalidOpcode);
}
}
0b101 => {
@@ -8372,6 +8375,11 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
instruction.opcode = Opcode::TESTUI;
instruction.operands[0] = OperandSpec::Nothing;
instruction.operand_count = 0;
+ } else {
+ instruction.opcode = Opcode::Invalid;
+ instruction.operands[0] = OperandSpec::Nothing;
+ instruction.operand_count = 0;
+ return Err(DecodeError::InvalidOpcode);
}
}
0b110 => {
diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index 8bd55c1..9d51ba4 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -1021,8 +1021,8 @@ fn read_vex_instruction<T: Iterator<Item=u8>>(opcode_map: VEXOpcodeMap, bytes: &
},
VEXOpcodePrefix::Prefix66 => {
match opc {
- 0x0a => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8),
- 0x0b => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8),
+// 0x0a => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8),
+// 0x0b => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8),
0x10 => (Opcode::VMOVUPD, if L {
VEXOperandCode::G_E_ymm
} else {