diff options
| author | iximeow <me@iximeow.net> | 2021-06-28 23:46:22 -0700 | 
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-06-28 23:46:22 -0700 | 
| commit | 4b95d712c7923741fb91ca38967038af83fd2035 (patch) | |
| tree | b65bbf19db07896e6be26d423077cfacc63cb1cb /src/long_mode | |
| parent | 0ef199f018cafeeb0334470328c417023ff702eb (diff) | |
remove old movsx/movzx-related memory size hacks
Diffstat (limited to 'src/long_mode')
| -rw-r--r-- | src/long_mode/display.rs | 82 | ||||
| -rw-r--r-- | src/long_mode/mod.rs | 39 | 
2 files changed, 30 insertions, 91 deletions
| diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs index 7532101..107eb94 100644 --- a/src/long_mode/display.rs +++ b/src/long_mode/display.rs @@ -405,9 +405,6 @@ const MNEMONICS: &[&'static str] = &[      "cvtss2sd",      "cvtdq2pd",      "lddqu", -    "movsx", -    "movsx", -    "movzx",      "movzx",      "movsx",      "movsxd", @@ -2830,10 +2827,7 @@ impl <T: fmt::Write, Y: YaxColors> Colorize<T, Y> for Opcode {              Opcode::IN |              Opcode::OUTS |              Opcode::OUT | -            Opcode::MOVSX_b | -            Opcode::MOVSX_w | -            Opcode::MOVZX_b | -            Opcode::MOVZX_w | +            Opcode::MOVZX |              Opcode::MOVSX |              Opcode::MOVSXD |              Opcode::FILD | @@ -3692,74 +3686,22 @@ impl <T: fmt::Write, Y: YaxColors> ShowContextual<u64, [Option<alloc::string::St          };          for i in 1..self.operand_count {              let i = i as usize; -            match self.opcode { -                Opcode::MOVSX_b | -                Opcode::MOVZX_b => { -                    match context.and_then(|xs| xs[i].as_ref()) { -                        Some(s) => { write!(out, ", {}", s)? } -                        None => { -                            match &self.operands[i] { -                                &OperandSpec::Nothing => { -                                    return Ok(()); -                                }, -                                &OperandSpec::RegMMM => { -                                    write!(out, ", ")?; -                                } -                                _ => { -                                    write!(out, ", byte ")?; -                                    if let Some(prefix) = self.segment_override_for_op(1) { -                                        write!(out, "{}:", prefix)?; -                                    } -                                } -                            } -                            let x = Operand::from_spec(self, self.operands[i]); -                            x.colorize(colors, out)? -                        } -                    } -                }, -                Opcode::MOVSX_w | -                Opcode::MOVZX_w => { -                    match context.and_then(|xs| xs[i].as_ref()) { -                        Some(s) => { write!(out, ", {}", s)? } -                        None => { -                            match &self.operands[i] { -                                &OperandSpec::Nothing => { -                                    return Ok(()); -                                }, -                                &OperandSpec::RegMMM => { -                                    write!(out, ", ")?; -                                } -                                _ => { -                                    write!(out, ", word ")?; -                                    if let Some(prefix) = self.segment_override_for_op(1) { -                                        write!(out, "{}:", prefix)?; -                                    } -                                } +            match context.and_then(|xs| xs[i].as_ref()) { +                Some(s) => { write!(out, ", {}", s)? } +                None => { +                    match &self.operands[i] { +                        &OperandSpec::Nothing => { +                            return Ok(()); +                        }, +                        _ => { +                            write!(out, ", ")?; +                            if let Some(prefix) = self.segment_override_for_op(1) { +                                write!(out, "{}:", prefix)?;                              }                              let x = Operand::from_spec(self, self.operands[i]);                              x.colorize(colors, out)?                          }                      } -                }, -                _ => { -                    match context.and_then(|xs| xs[i].as_ref()) { -                        Some(s) => { write!(out, ", {}", s)? } -                        None => { -                            match &self.operands[i] { -                                &OperandSpec::Nothing => { -                                    return Ok(()); -                                }, -                                _ => { -                                    write!(out, ", ")?; -                                    if let Some(prefix) = self.segment_override_for_op(1) { -                                        write!(out, "{}:", prefix)?; -                                    } -                                    let x = Operand::from_spec(self, self.operands[i]); -                                    x.colorize(colors, out)? -                                } -                            } -                        } -                    }                  }              }          } diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 9fee5b9..29a76a8 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -865,7 +865,7 @@ const REGISTER_CLASS_NAMES: &[&'static str] = &[  ///     .decode(movsx_eax_cl.into_iter().cloned())  ///     .expect("can decode");  /// -/// assert_eq!(instruction.opcode(), Opcode::MOVSX_b); +/// assert_eq!(instruction.opcode(), Opcode::MOVSX);  ///  /// fn show_register_class_info(regclass: RegisterClass) {  ///     match regclass { @@ -1104,10 +1104,7 @@ pub enum Opcode {      CVTSS2SD,      CVTDQ2PD,      LDDQU, -    MOVSX_b, -    MOVSX_w, -    MOVZX_b, -    MOVZX_w, +    MOVZX,      MOVSX,      MOVSXD,      SAR, @@ -5860,16 +5857,16 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord {              0xb3 => OpcodeRecord(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv),              0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M),              0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), -            0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_b), OperandCode::Gv_Eb), -            0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_w), OperandCode::Gv_Ew), +            0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), +            0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew),              0xb8 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),              0xb9 => OpcodeRecord(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev),              0xba => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba),              0xbb => OpcodeRecord(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv),              0xbc => OpcodeRecord(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev),              0xbd => OpcodeRecord(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), -            0xbe => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX_b), OperandCode::Gv_Eb), -            0xbf => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX_w), OperandCode::Gv_Ew), +            0xbe => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), +            0xbf => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew),  // 0xc0              0xc0 => OpcodeRecord(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb),              0xc1 => OpcodeRecord(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), @@ -6137,16 +6134,16 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord {              0xb3 => OpcodeRecord(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv),              0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M),              0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), -            0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_b), OperandCode::Gv_Eb), -            0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_w), OperandCode::Gv_Ew), +            0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), +            0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew),              0xb8 => OpcodeRecord(Interpretation::Instruction(Opcode::POPCNT), OperandCode::Gv_Ev),              0xb9 => OpcodeRecord(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev),              0xba => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba),              0xbb => OpcodeRecord(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv),              0xbc => OpcodeRecord(Interpretation::Instruction(Opcode::TZCNT), OperandCode::Gv_Ev),              0xbd => OpcodeRecord(Interpretation::Instruction(Opcode::LZCNT), OperandCode::Gv_Ev), -            0xbe => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX_b), OperandCode::Gv_Eb), -            0xbf => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX_w), OperandCode::Gv_Ew), +            0xbe => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), +            0xbf => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew),  // 0xc0              0xc0 => OpcodeRecord(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb),              0xc1 => OpcodeRecord(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), @@ -6411,16 +6408,16 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord {              0xb3 => OpcodeRecord(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv),              0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M),              0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), -            0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_b), OperandCode::Gv_Eb), -            0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_w), OperandCode::Gv_Ew), +            0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), +            0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew),              0xb8 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),              0xb9 => OpcodeRecord(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev),              0xba => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba),              0xbb => OpcodeRecord(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv),              0xbc => OpcodeRecord(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev),              0xbd => OpcodeRecord(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), -            0xbe => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX_b), OperandCode::Gv_Eb), -            0xbf => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX_w), OperandCode::Gv_Ew), +            0xbe => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), +            0xbf => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew),  // 0xc0              0xc0 => OpcodeRecord(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb),              0xc1 => OpcodeRecord(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), @@ -6693,16 +6690,16 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord {              0xb3 => OpcodeRecord(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv),              0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M),              0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), -            0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_b), OperandCode::Gv_Eb), -            0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_w), OperandCode::Gv_Ew), +            0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), +            0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew),              0xb8 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // JMPE, ITANIUM              0xb9 => OpcodeRecord(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev),              0xba => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba),              0xbb => OpcodeRecord(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv),              0xbc => OpcodeRecord(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev),              0xbd => OpcodeRecord(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), -            0xbe => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX_b), OperandCode::Gv_Eb), -            0xbf => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX_w), OperandCode::Gv_Ew), +            0xbe => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), +            0xbf => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew),  // 0xc0              0xc0 => OpcodeRecord(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), | 
