fix handling of lar/lsl source register

1 files changed, 27 insertions, 6 deletions

diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 71b2373..14f782c 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -5037,6 +5037,7 @@ enum OperandCase {
     AX_Ib,
     Ib_AL,
     Ib_AX,
+    Gv_Ew_LAR,
     Gv_Ew_LSL,
     Gdq_Ev,
     Gv_Ev_Ib,
@@ -5374,6 +5375,7 @@ enum OperandCode {
     Zv_Ivq_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Ivq_R, 7).bits(),
     Gv_Eb = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Eb).bits(),
     Gv_Ew = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew).bits(),
+    Gv_Ew_LAR = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew_LAR).bits(),
     Gv_Ew_LSL = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew_LSL).bits(),
     Gdq_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gdq_Ed).bits(),
     Gd_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gd_Ed).bits(),
@@ -8009,11 +8011,30 @@ fn read_operands<
             instruction.regs[1].bank = RegisterBank::MM;
             instruction.regs[1].num &= 0b111;
         },
+        OperandCase::Gv_Ew_LAR => {
+            instruction.operands[1] = mem_oper;
+            // lar is weird. a segment selector is taken from the source register, which means
+            // either we read the low 16-bits of a register or read 16 bits from a memory operand.
+            // for whatever reason, the intel manual writes a source register as a dword/qword for
+            // larger modes even though the upper 16 bits would be ignored.
+            //
+            // so the registers are correct by the time we're here, we might just need to override
+            // mem size as well.
+            if instruction.operands[1] != OperandSpec::RegMMM {
+                instruction.mem_size = 2;
+            }
+            instruction.regs[0].bank = self.vqp_size();
+        },
         OperandCase::Gv_Ew_LSL => {
             instruction.operands[1] = mem_oper;
-            // lsl is weird. the full register width is written, but only the low 16 bits are used.
+            // lsl is weird. a segment selector is taken from the source register, which means
+            // either we read the low 16-bits of a register or read 16 bits from a memory operand.
+            // for whatever reason, the intel manual writes a source register as a dword for larger
+            // modes even though the upper 16 bits would be ignored.
             if instruction.operands[1] == OperandSpec::RegMMM {
-                instruction.regs[1].bank = RegisterBank::D;
+                if instruction.regs[1].bank == RegisterBank::Q {
+                    instruction.regs[1].bank = RegisterBank::D;
+                }
             } else {
                 instruction.mem_size = 2;
             }
@@ -10869,7 +10890,7 @@ fn read_modrm<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpeax_
 const REPNZ_0F_CODES: [OpcodeRecord; 256] = [
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01),
-    OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew),
+    OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing),
@@ -11145,7 +11166,7 @@ const REPNZ_0F_CODES: [OpcodeRecord; 256] = [
 const REP_0F_CODES: [OpcodeRecord; 256] = [
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01),
-    OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew),
+    OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing),
@@ -11421,7 +11442,7 @@ const REP_0F_CODES: [OpcodeRecord; 256] = [
 const OPERAND_SIZE_0F_CODES: [OpcodeRecord; 256] = [
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01),
-    OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew),
+    OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing),
@@ -11694,7 +11715,7 @@ const OPERAND_SIZE_0F_CODES: [OpcodeRecord; 256] = [
 const NORMAL_0F_CODES: [OpcodeRecord; 256] = [
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01),
-    OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew),
+    OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
     OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing),