diff options
| author | iximeow <me@iximeow.net> | 2023-02-11 17:11:09 -0800 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2023-07-04 19:01:38 -0700 |
| commit | 113dcc53cef5d90b667fe150c37ca82ac11bb45f (patch) | |
| tree | 47460e37e56c13f42b31d695fef44551cbdc907b /src/long_mode | |
| parent | c0769d677afdda22c1a8bbd2f54db19004c0e0b3 (diff) | |
new record: 50.56cpi (2290ms)
Diffstat (limited to 'src/long_mode')
| -rw-r--r-- | src/long_mode/mod.rs | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 2f4b799..30fa7ef 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -7152,7 +7152,6 @@ fn read_operands< } let mut modrm = 0; - let mut opwidth = 0; let mut mem_oper = OperandSpec::Nothing; if operand_code.has_read_E() { let bank; @@ -7161,11 +7160,9 @@ fn read_operands< // further, this is an vdq E bank = instruction.prefixes.vqp_size(); instruction.mem_size = bank as u8; - opwidth = bank as u8; } else { bank = instruction.prefixes.rb_size(); instruction.mem_size = 1; - opwidth = 1; }; modrm = read_modrm(words)?; instruction.regs[0].bank = bank; @@ -7256,6 +7253,8 @@ fn read_operands< InnerDescription::Misc("opcode selects `eax` operand") .with_id(opcode_start + 2) ); + // TODO: hmm + let opwidth = 0; if opwidth == 2 { sink.record( opcode_start + 3, @@ -7387,6 +7386,7 @@ fn read_operands< InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); + let opwidth = instruction.regs[0].bank as u8; if opwidth == 8 { instruction.imm = read_imm_signed(words, 4)? as u64; sink.record( @@ -7412,8 +7412,8 @@ fn read_operands< }; }, OperandCase::MovI8 => { - if (modrm & 0b00111000) != 0 { - if modrm == 0xf8 { + if instruction.regs[0].num & 0b0111 != 0 { + if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XABORT; instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( @@ -7448,8 +7448,9 @@ fn read_operands< } OperandCase::MovIv => { - if (modrm & 0b00111000) != 0 { - if modrm == 0xf8 { + let opwidth = instruction.regs[0].bank as u8; + if instruction.regs[0].num & 0b0111 != 0 { + if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XBEGIN; instruction.imm = if opwidth == 2 { let imm = read_imm_signed(words, 2)? as i16 as i64 as u64; @@ -7502,7 +7503,7 @@ fn read_operands< }, OperandCase::BitwiseWithI8 => { instruction.operands[0] = mem_oper; - instruction.opcode = bitwise_opcode_map((modrm >> 3) & 7); + instruction.opcode = bitwise_opcode_map(instruction.regs[0].num & 0b0111); sink.record( modrm_start + 3, modrm_start + 5, @@ -7558,6 +7559,7 @@ fn read_operands< instruction.operands[1] = OperandSpec::RegRRR; }, OperandCase::ModRM_0xf6_0xf7 => { + let opwidth = instruction.regs[0].bank as u8; instruction.operands[0] = mem_oper; const TABLE: [Opcode; 8] = [ Opcode::TEST, Opcode::TEST, Opcode::NOT, Opcode::NEG, |