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| author | iximeow <me@iximeow.net> | 2021-01-15 18:40:31 -0800 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-01-15 18:41:16 -0800 |
| commit | 6232e8b1daf7067cb2e8065687530d5f88ecb46d (patch) | |
| tree | 864b839a32f0154579a6a4c79ca227045f1a202e /src/long_mode | |
| parent | d8083b08dc987adeda73fb13298383c6cf519596 (diff) | |
support xchg AX/reg0.1.5
Diffstat (limited to 'src/long_mode')
| -rw-r--r-- | src/long_mode/mod.rs | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index f9be9ab..909157b 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -6079,6 +6079,20 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, } 1 => { // Zv_AX + let opwidth = imm_width_from_prefixes_64(SizeCode::vqp, instruction.prefixes); + let bank = if opwidth == 4 { + RegisterBank::D + } else if opwidth == 2 { + RegisterBank::W + } else { + RegisterBank::Q + }; + instruction.modrm_rrr = + RegSpec::from_parts(0, instruction.prefixes.rex().b(), bank); + instruction.operands[1] = OperandSpec::RegMMM; + instruction.modrm_mmm = + RegSpec::from_parts(reg, instruction.prefixes.rex().b(), bank); + instruction.operand_count = 2; } 2 => { // these are Zb_Ib_R |