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authoriximeow <me@iximeow.net>2026-05-25 19:21:31 +0000
committeriximeow <me@iximeow.net>2026-05-25 19:24:01 +0000
commitfe6b2b898aee944ba3490c35f4aed4d155485c0e (patch)
tree984496e7ec908c43272d591db12a566c49ea07a2 /src/protected_mode/mod.rs
parentb43f483a50f650dbf385d2d55d0d38171f08e32b (diff)
push/pop width in 16/32-bit modes are receptive to operand width prefix
Diffstat (limited to 'src/protected_mode/mod.rs')
-rw-r--r--src/protected_mode/mod.rs3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index 17fd883..3036620 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -5774,13 +5774,14 @@ fn read_operands<
0 => {
// these are Zv_R
let bank = if !instruction.prefixes.operand_size() {
+ instruction.mem_size = 4;
RegisterBank::D
} else {
+ instruction.mem_size = 2;
RegisterBank::W
};
instruction.regs[0] =
RegSpec::from_parts(reg, bank);
- instruction.mem_size = 4;
sink.record(
opcode_start + 0,
opcode_start + 2,